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Publications of Author

1. Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin
   A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:20250-20255 [Conf]
   
2. Adel Baganne, Jean Luc Philippe, Eric Martin
   Hardware interface design for real time embedded systems. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1997, pp:58-63 [Conf]
   
3. S. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin
   Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1999, pp:334-335 [Conf]
   
4. Philippe Coussy, Adel Baganne, Eric Martin
   A design methodology for IP integration. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2002, pp:711-714 [Conf]
   
5. Philippe Coussy, Adel Baganne, Eric Martin
   Communication and Timing Constraints Analysis for IP Design and Integration. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2003, pp:38-43 [Conf]
   
6. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
   Constrained algorithmic IP design for system-on-chip. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:2, pp:94-105 [Journal]
   
7. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
   A formal method for hardware IP design and integration under I/O and timing constraints. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:29-53 [Journal]
   
8. Mehrez Marzougui, Mohamed Abid, Adel Baganne, Rached Tourki
   Co-simulation and communication synthesis approach for intellectual properties based SoCs. [Citation Graph (0, 0)][DBLP]
   Computers & Electrical Engineering, 2004, v:30, n:5, pp:361-381 [Journal]
   
9. 
   A Reconfigurable Implementation of the New Secure Hash Algorithm. [Citation Graph (, )][DBLP]