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Publications of Author

1. Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge
   Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:650-651 [Conf]
   
2. Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge
   Total leakage optimization strategies for multi-level caches. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:381-384 [Conf]
   
3. Nam Sung Kim, David Blaauw, Trevor N. Mudge
   Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:627-632 [Conf]
   
4. Nam Sung Kim, Trevor N. Mudge
   Reducing register ports using delayed write-back queues and operand pre-fetch. [Citation Graph (0, 0)][DBLP]
   ICS, 2003, pp:172-182 [Conf]
   
5. Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor N. Mudge
   Drowsy Caches: Simple Techniques for Reducing Leakage Power. [Citation Graph (0, 0)][DBLP]
   ISCA, 2002, pp:148-157 [Conf]
   
6. Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge
   Microarchitectural power modeling techniques for deep sub-micron microprocessors. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:212-217 [Conf]
   
7. Nam Sung Kim, Trevor N. Mudge
   The microarchitecture of a low power register file. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:384-389 [Conf]
   
8. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge
   Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. [Citation Graph (0, 0)][DBLP]
   MICRO, 2003, pp:7-18 [Conf]
   
9. Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge
   Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. [Citation Graph (0, 0)][DBLP]
   MICRO, 2002, pp:219-230 [Conf]
   
10. Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan
    Leakage Current: Moore's Law Meets Static Power. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:68-75 [Journal]
    
11. Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner
    Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:10-20 [Journal]
    
12. Nam Sung Kim, David Blaauw, Trevor N. Mudge
    Quantitative analysis and optimization techniques for on-chip cache leakage power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1147-1156 [Journal]
    
13. Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge
    Circuit and microarchitectural techniques for reducing cache leakage power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:167-184 [Journal]
    
14. Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge
    Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
15. 
    Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. [Citation Graph (, )][DBLP]
    
    
16. 
    On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology. [Citation Graph (, )][DBLP]
    
    
17. 
    Yield-driven near-threshold SRAM design. [Citation Graph (, )][DBLP]
    
    
18. 
    Optimizing total power of many-core processors considering voltage scaling limit and process variations. [Citation Graph (, )][DBLP]
    
    
19. 
    Statistical static timing analysis considering leakage variability in power gated designs. [Citation Graph (, )][DBLP]
    
    
20. 
    Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors. [Citation Graph (, )][DBLP]
    
    
21. 
    Frequency and yield optimization using power gates in power-constrained designs. [Citation Graph (, )][DBLP]
    
    
22. 
    Workload-adaptive process tuning strategy for power-efficient multi-core processors. [Citation Graph (, )][DBLP]
    
    
23. 
    Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits. [Citation Graph (, )][DBLP]