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Publications of Author

1. J. Balachandran, Steven Brebels, G. Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne
   Analysis and modeling of power grid transmission lines. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:33-38 [Conf]
   
2. C. Truzzi, Eric Beyne, E. Ringoot, J. Peeters
   Signal propagation in high-speed MCM circuits. [Citation Graph (0, 0)][DBLP]
   ICCD, 1995, pp:12-17 [Conf]
   
3. J. Balachandran, Steven Brebels, G. Carchon, Walter De Raedt, Eric Beyne, M. Kuijk, Bart Nauwelaers
   Constant Impedance Scaling Paradigm for Scaling LC transmission lines. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:387-392 [Conf]
   
4. J. Balachandran, Steven Brebels, G. Carchon, M. Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne
   Constant impedance scaling paradigm for interconnect synthesis. [Citation Graph (0, 0)][DBLP]
   SLIP, 2006, pp:99-105 [Conf]
   
5. J. Balachandran, Steven Brebels, G. Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne
   Package level interconnect options. [Citation Graph (0, 0)][DBLP]
   SLIP, 2005, pp:21-27 [Conf]
   
6. Eric Beyne
   Tutorial T7A: Advanced IC Packaging. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:10- [Conf]
   
7. J. Balachandran, Steven Brebels, G. Carchon, M. Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne
   Wafer-level package interconnect options. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:654-659 [Journal]
   
8. Bart Vandevelde, Dominiek Degryse, Eric Beyne, Eric Roose, Dorina Corlatan, Guido Swaelen, Geert Willems, Filip Christiaens, Alcatel Bell, Dirk Vandepitte
   Modified micro-macro thermo-mechanical modelling of ceramic ball grid array packages. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2003, v:43, n:2, pp:307-318 [Journal]
   
9. Arun Chandrasekhar, Steven Brebels, Serguei Stoukatch, Eric Beyne, Walter De Raedt, Bart Nauwelaers
   The influence of packaging materials on RF performance. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2003, v:43, n:3, pp:351-357 [Journal]
   
10. Hong Meng Ho, Wai Lam, Serguei Stoukatch, Petar Ratchev, Charles J. Vath, Eric Beyne
    Direct gold and copper wires bonding on copper. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:6, pp:913-923 [Journal]
    
11. Bart Vandevelde, Mario Gonzalez, Paresh Limaye, Petar Ratchev, Eric Beyne
    Thermal cycling reliability of SnAgCu and SnPb solder joints: A comparison for several IC-packages. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2007, v:47, n:2-3, pp:259-265 [Journal]
    
12. 
    Impact of 3D design choices on manufacturing cost. [Citation Graph (, )][DBLP]
    
    
13. 
    3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). [Citation Graph (, )][DBLP]
    
    
14. 
    Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. [Citation Graph (, )][DBLP]