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Chunduri Rama Mohan:
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Publications of Author
- Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:668-669 [Conf]
- Sayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni
Formal verification coverage: computing the coverage gap between temporal specifications. [Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:198-203 [Conf]
- Chunduri Rama Mohan, Partha Pratim Chakrabarti
A new approach for factorizing FSM's. [Citation Graph (0, 0)][DBLP] ICCAD, 1994, pp:698-701 [Conf]
- Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. [Citation Graph (0, 0)][DBLP] VLSI Design, 2004, pp:109-114 [Conf]
- Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model. [Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:201-206 [Conf]
- Chunduri Rama Mohan, Partha Pratim Chakrabarti
A New Approach to Synthesis of PLA-Based FSM's. [Citation Graph (0, 0)][DBLP] VLSI Design, 1994, pp:373-378 [Conf]
- Chunduri Rama Mohan, Partha Pratim Chakrabarti
Combined optimization of area and testability during state assignment of PLA-based FSM's. [Citation Graph (0, 0)][DBLP] VLSI Design, 1995, pp:408-413 [Conf]
- Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose
Combining State Assignment with PLA Folding. [Citation Graph (0, 0)][DBLP] VLSI Design, 1993, pp:9-14 [Conf]
- Chunduri Rama Mohan, S. Mitra, Partha Pal Chaudhuri
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. [Citation Graph (0, 0)][DBLP] VLSI Design, 1997, pp:547-563 [Conf]
- Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama Mohan
An ECO Technique for Removing Crosstalk Violations in Clock Networks. [Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:283-288 [Conf]
- Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni
Design-Intent Coverage - A New Paradigm for Formal Property Verification. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1922-1934 [Journal]
- Chunduri Rama Mohan, Partha Pratim Chakrabarti
EARTH: combined state assignment of PLA-based FSM's targeting area and testability. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:727-731 [Journal]
Cohesive Coverage Management for Simulation and Formal Property Verification. [Citation Graph (, )][DBLP]
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