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Behnam Amelifard: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:995-1000 [Conf]
  2. Behnam Amelifard, Ali Afzali-Kusha, Ahmad Khademzadeh
    Enhancing the efficiency of cluster voltage scaling technique for low-power application. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1666-1669 [Conf]
  3. Mohammad Taherzadeh-Sani, Ali Abbasian, Behnam Amelifard, Ali Afzali-Kusha
    Modeling of MOS transistors based on genetic algorithm and simulated annealing. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6218-6221 [Conf]
  4. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Low-power fanout optimization using multiple threshold voltage inverters. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:95-98 [Conf]
  5. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Low-power fanout optimization using MTCMOS and multi-Vt techniques. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:334-337 [Conf]
  6. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:148-152 [Conf]
  7. Behnam Amelifard, Massoud Pedram, Farzan Fallah
    Low-leakage SRAM Design with Dual V_t Transistors. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:729-734 [Conf]
  8. Behnam Amelifard, Massoud Pedram
    Optimal Selection of Voltage Regulator Modules in a Power Delivery Network. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:168-173 [Conf]

  9. A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect. [Citation Graph (, )][DBLP]


  10. NBTI-aware flip-flop characterization and design. [Citation Graph (, )][DBLP]


  11. Power optimal MTCMOS repeater insertion for global buses. [Citation Graph (, )][DBLP]


  12. Design of an efficient power delivery network in an soc to enable dynamic power management. [Citation Graph (, )][DBLP]


  13. A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops. [Citation Graph (, )][DBLP]


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