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Edson I. Moreno: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:62-63 [Conf]
  2. Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara
    From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:355-0 [Conf]
  3. César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes
    Evaluation of Algorithms for Low Energy Mapping onto NoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:389-392 [Conf]
  4. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

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