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Lorena Anghel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lorena Anghel, Michael Nicolaidis
    Cost Reduction and Evaluation of a Temporary Faults Detecting Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:591-598 [Conf]
  2. Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
    New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:99-107 [Conf]
  3. Lorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco
    Coupling Different Methodologies to Validate Obsolete Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:250-255 [Conf]
  4. Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary
    Preliminary Validation of an Approach Dealing with Processor Obsolescence. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:493-0 [Conf]
  5. Michael Nicolaidis, Nadir Achouri, Lorena Anghel
    A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:459-466 [Conf]
  6. Michael Nicolaidis, Nadir Achouri, Lorena Anghel
    Memory Built-In Self-Repair for Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:94-0 [Conf]
  7. Raoul Velazco, Lorena Anghel, S. Saleh
    A Methodology for Test Replacement Solutions of Obsolete Processors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:209-213 [Conf]
  8. Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert
    Evaluation of SET and SEU Effects at Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:309-312 [Conf]
  9. Lorena Anghel, Michael Nicolaidis
    Simulation and Mitigation of Single Event Effects. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:81- [Conf]
  10. G. Hubert, A. Bougerol, F. Miller, N. Buard, L. Anghel, T. Carriere, F. Wrobel, R. Gaillard
    Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:63-74 [Conf]
  11. Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel
    Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:165-172 [Conf]
  12. Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis
    On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:29-34 [Conf]
  13. Lorena Anghel, Michael Nicolaidis, Nadine Buard
    From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately? [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:85- [Conf]
  14. Lorena Anghel, Nadir Achouri, Michael Nicolaidis
    Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie. [Citation Graph (0, 0)][DBLP]
    PRDC, 2004, pp:315-320 [Conf]
  15. Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal
    Self-Checking Circuits versus Realistic Faults in Very Deep Submicron. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:55-66 [Conf]
  16. Th. Calin, Lorena Anghel, Michael Nicolaidis
    Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:135-142 [Conf]
  17. Michael Nicolaidis, Nadir Achouri, Lorena Anghel
    A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:313-318 [Conf]
  18. C. Rusu, A. Bougerol, L. Anghel, C. Weulersse, N. Buard, S. Benhammadi, N. Renaud, G. Hubert, F. Wrobel, T. Carriere, R. Gaillard
    Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:137-145 [Conf]
  19. Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve Saleh
    Essential Fault-Tolerance Metrics for NoC Infrastructures. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:37-42 [Conf]
  20. Lorena Anghel, Michael Nicolaidis
    Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    IWANN, 2007, pp:422-429 [Conf]
  21. Cristiano Lazzari, Lorena Anghel, Ricardo Reis
    A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:331-344 [Conf]
  22. Michael Nicolaidis, Lorena Anghel, Nadir Achouri
    Memory Defect Tolerance Architectures for Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:445-455 [Journal]

  23. HOT TOPIC - Concurrent SoC development and end-to-end planning. [Citation Graph (, )][DBLP]

  24. Error resilience of intra-die and inter-die communication with 3D spidergon STNoC. [Citation Graph (, )][DBLP]

  25. Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems. [Citation Graph (, )][DBLP]

  26. Digital Implementation of a BIST Method based on Binary Observations. [Citation Graph (, )][DBLP]

  27. Communication Aware Recovery Configurations for Networks-on-Chip. [Citation Graph (, )][DBLP]

  28. Improving the scalability of checkpoint recovery for networks-on-chip. [Citation Graph (, )][DBLP]

  29. An effective approach to detect logic soft errors in digital circuits based on GRAAL. [Citation Graph (, )][DBLP]

  30. Efficient timing closure with a transistor level design flow. [Citation Graph (, )][DBLP]

  31. Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. [Citation Graph (, )][DBLP]

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