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Alberto Bosio: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Automatic march tests generations for static linked faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1258-1263 [Conf]
  2. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:157-158 [Conf]
  3. Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    A Mixed Approach for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:239-242 [Conf]
  4. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Automatic March Tests Generation for Multi-Port SRAMs. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:385-392 [Conf]
  5. Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    DERRIC: A Tool for Unified Logic Diagnosis. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:13-20 [Conf]
  6. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    A 22n March Test for Realistic Static Linked Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:49-54 [Conf]

  7. Delay Fault Diagnosis in Sequential Circuits. [Citation Graph (, )][DBLP]


  8. A statistical simulation method for reliability analysis of SRAM core-cells. [Citation Graph (, )][DBLP]


  9. An efficient fault simulation technique for transition faults in non-scan sequential circuits. [Citation Graph (, )][DBLP]


  10. SoC Symbolic Simulation: a case study on delay fault testing. [Citation Graph (, )][DBLP]


  11. Comprehensive bridging fault diagnosis based on the SLAT paradigm. [Citation Graph (, )][DBLP]


  12. Improving Diagnosis Resolution without Physical Information. [Citation Graph (, )][DBLP]


  13. An Exact and Efficient Critical Path Tracing Algorithm. [Citation Graph (, )][DBLP]


  14. Impact of Resistive-Bridging Defects in SRAM Core-Cell. [Citation Graph (, )][DBLP]


  15. A Functional Verification Based Fault Injection Environment. [Citation Graph (, )][DBLP]


  16. Using TMR Architectures for Yield Improvement. [Citation Graph (, )][DBLP]


  17. Yield Improvement, Fault-Tolerance to the Rescue?. [Citation Graph (, )][DBLP]


  18. A Modular Memory BIST for Optimized Memory Repair. [Citation Graph (, )][DBLP]


  19. A case study on logic diagnosis for System-on-Chip. [Citation Graph (, )][DBLP]


  20. Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. [Citation Graph (, )][DBLP]


  21. Setting test conditions for improving SRAM reliability. [Citation Graph (, )][DBLP]


  22. A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. [Citation Graph (, )][DBLP]


  23. Are IEEE-1500-Compliant Cores Really Compliant to the Standard?. [Citation Graph (, )][DBLP]


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