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Publications of Author

1. Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
   Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:464-465 [Conf]
   
2. José Luis Rosselló, V. Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
   A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:206-211 [Conf]
   
3. José Luis Rosselló, Jaume Segura
   A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:954-961 [Conf]
   
4. José Luis Rosselló, Jaume Segura
   A compact model to identify delay faults due to crosstalk. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:902-906 [Conf]
   
5. José Luis Rosselló, Jaume Segura
   Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2001, pp:494-0 [Conf]
   
6. Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi
   Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:1276-1284 [Conf]
   
7. José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
   Leakage Power Characterization Considering Process Variations. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2006, pp:66-74 [Conf]
   
8. José Luis Rosselló, Sebastià A. Bota, Jaume Segura
   Compact Static Power Model of Complex CMOS Gates. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2005, pp:348-354 [Conf]
   
9. José Luis Rosselló, Jaume Segura
   A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2002, pp:219-228 [Conf]
   
10. José Luis Rosselló, Jaume Segura
    A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:51-59 [Conf]
    
11. Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
    Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:358-363 [Conf]
    
12. Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura
    Impact of Thermal Gradients on Clock Skew and Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:414-424 [Journal]
    
13. José Luis Rosselló, Jaume Segura
    Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:433-448 [Journal]
    
14. José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
    Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1271-1276 [Conf]
    
15. Sebstatià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
    Smart Temperature Sensor for Thermal Testing of Cell-Based ICs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
16. José Luis Rosselló, V. Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
    A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
17. 
    Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis. [Citation Graph (, )][DBLP]
    
    
18. 
    A Fully CMOS Low-Cost Chaotic Neural Network. [Citation Graph (, )][DBLP]
    
    
19. 
    Using stochastic logic for efficient pattern recognition analysis. [Citation Graph (, )][DBLP]
    
    
20. 
    Practical Hardware Implementation of Self-configuring Neural Networks. [Citation Graph (, )][DBLP]