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Wim Dehaene: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha Chandrakasan, Wim Dehaene
    Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:196-201 [Conf]
  2. Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
    Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:36-42 [Conf]
  3. Ali Sayinta, Gorkem Canverdi, Marc Pauwels, Amer Alshawa, Wim Dehaene
    A Mixed Abstraction Level Co-Simulation Case Study Using SystemC for System on Chip Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20095-20100 [Conf]
  4. Yves Vanderperren, Wim Dehaene
    UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:716-717 [Conf]
  5. Yves Vanderperren, Wim Dehaene
    From UML/SysML to Matlab/Simulink: current state and future perspectives. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:93- [Conf]
  6. Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor, Karen Maex
    Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:914-919 [Conf]
  7. Wolfgang Mueller, Alberto Rosti, Sara Bocchio, Elvinia Riccobene, Patrizia Scandurra, Wim Dehaene, Yves Vanderperren
    UML for ESL design: basic principles, tools, and applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:73-80 [Conf]
  8. Marian Verhelst, Wim Vereecken, Michiel Steyaert, Wim Dehaene
    Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:280-285 [Conf]
  9. Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene
    Statistically Aware SRAM Memory Array Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:25-30 [Conf]
  10. Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene
    On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:71-76 [Conf]
  11. Hua Wang, Miguel Miranda, Antonis Papanikolaou, Francky Catthoor, Wim Dehaene
    Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1127-1135 [Journal]
  12. Bruno Bougard, Sofie Pollin, Antoine Dejonghe, Francky Catthoor, Wim Dehaene
    Cross-layer power management in wireless networks and consequences on system-level architecture. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2006, v:86, n:8, pp:1792-1803 [Journal]
  13. Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
    Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  14. Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha Chandrakasan, Wim Dehaene
    Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  15. A subsampling pulsed UWB demodulator based on a flexible complex SVD. [Citation Graph (, )][DBLP]


  16. ActivaSC: a highly efficient and non-intrusive extension for activity-based analysis of SystemC models. [Citation Graph (, )][DBLP]


  17. System-level power/performance evaluation of 3D stacked DRAMs for mobile applications. [Citation Graph (, )][DBLP]


  18. A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. [Citation Graph (, )][DBLP]


  19. An RDL-configurable 3D memory tier to replace on-chip SRAM. [Citation Graph (, )][DBLP]


  20. A Low Power, Reconfigurable IR-UWB System. [Citation Graph (, )][DBLP]


  21. A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter. [Citation Graph (, )][DBLP]


  22. A low-power mixing DAC IR-UWB-receiver. [Citation Graph (, )][DBLP]


  23. The SysML profile for embedded system modelling. [Citation Graph (, )][DBLP]


  24. SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks. [Citation Graph (, )][DBLP]


  25. 3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). [Citation Graph (, )][DBLP]


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