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Vincent Beroulle: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
    On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1120- [Conf]
  2. Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre
    Mutation Sampling Technique for the Generation of Structural Test Data. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1022-1023 [Conf]
  3. Youssef Serrestou, Vincent Beroulle, Chantal Robach
    How to Improve a Set of Design Validation Data by Using Mutation-based Test. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:77-78 [Conf]
  4. Yves Joannon, Vincent Beroulle, Rami Khouri, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro
    Behavioral Modeling of WCDMA Transceiver with VHDL-AMS Language. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:113-118 [Conf]
  5. Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand
    Design-for-Test of Asynchronous Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:163-167 [Conf]
  6. Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
    Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:461-472 [Conf]
  7. Vincent Beroulle, Laurent Latorre, M. Dardalhon, C. Oudea, G. Perez, F. Pressecq, Pascal Nouet
    Impact of Technology Spreading on MEMS design Robustness. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:241-251 [Conf]
  8. Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
    Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:439-444 [Conf]
  9. Laurent Latorre, Vincent Beroulle, Pascal Nouet
    Design of CMOS MEMS based on mechanical resonators using a RF simulation approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:962-967 [Journal]
  10. Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach
    A DFT Architecture for Asynchronous Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:219-224 [Conf]
  11. Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach
    Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:216- [Conf]
  12. Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre
    Mutation Sampling Technique for the Generation of Structural Test Data [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  13. Functional Verification of RTL Designs driven by Mutation Testing metrics. [Citation Graph (, )][DBLP]


  14. Qualification of behavioral level design validation for AMS & RF SoCs. [Citation Graph (, )][DBLP]


  15. Impact of hardware emulation on the verification quality improvement. [Citation Graph (, )][DBLP]


  16. A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. [Citation Graph (, )][DBLP]


  17. Decreasing Test Qualification Time in AMS and RF Systems. [Citation Graph (, )][DBLP]


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