Functional Verification of RTL Designs driven by Mutation Testing metrics. [Citation Graph (, )][DBLP]
Qualification of behavioral level design validation for AMS & RF SoCs. [Citation Graph (, )][DBLP]
Impact of hardware emulation on the verification quality improvement. [Citation Graph (, )][DBLP]
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. [Citation Graph (, )][DBLP]
Decreasing Test Qualification Time in AMS and RF Systems. [Citation Graph (, )][DBLP]
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