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Pedro J. Gil: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sara Blanc, J. Gracia, Pedro J. Gil
    Experiences during the Experimental Validation of the Time-Triggered Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:256-261 [Conf]
  2. Sara Blanc, J. Gracia, Pedro J. Gil
    A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:254-262 [Conf]
  3. J. C. Baraza, J. Gracia, Daniel Gil, Pedro J. Gil
    A Prototype of a VHDL-Based Fault Injection Tool. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:396-404 [Conf]
  4. J. Gracia, J. C. Baraza, Daniel Gil, Pedro J. Gil
    Comparison and Application of Different VHDL-Based Fault Injection Techniques. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:233-241 [Conf]
  5. David de Andrés, Juan Carlos Ruiz, Daniel Gil, Pedro J. Gil
    Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems. [Citation Graph (0, 0)][DBLP]
    DSN, 2006, pp:291-300 [Conf]
  6. Juan-Carlos Ruiz-Garcia, Pedro Yuste, Pedro J. Gil, Lenin Lemus
    On Benchmarking the Dependability of Automotive Engine Control Applications. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:857-866 [Conf]
  7. Pedro Yuste, David de Andrés, Lenin Lemus, Juan José Serrano, Pedro J. Gil
    INERTE: Integrated NExus-Based Real-Time Fault Injection Tool for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSN, 2003, pp:669- [Conf]
  8. David de Andrés, José Albaladejo, Lenin Lemus, Pedro J. Gil
    Fast Run-Time Reconfiguration for SEU Injection. [Citation Graph (0, 0)][DBLP]
    EDCC, 2005, pp:230-245 [Conf]
  9. Daniel Gil, J. Gracia, J. C. Baraza, Pedro J. Gil
    Impact of Faults in Combinational Logic of Commercial Microcontrollers. [Citation Graph (0, 0)][DBLP]
    EDCC, 2005, pp:379-390 [Conf]
  10. Daniel Gil, R. Martínez, J. V. Busquets, J. C. Baraza, Pedro J. Gil
    Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:191-208 [Conf]
  11. Vicente Santonja, Marina Alonso, Xavier Molero, Juan José Serrano, Pedro J. Gil, Rafael Ors
    Dependability Models of RAID Using Stochastic Activity Networks. [Citation Graph (0, 0)][DBLP]
    EDCC, 1996, pp:141-158 [Conf]
  12. Lenin Lemus, David de Andrés, Pedro J. Gil
    An alternative to unify performance and reliability analysis of industrial applications. [Citation Graph (0, 0)][DBLP]
    ESM, 2000, pp:326-330 [Conf]
  13. Daniel Gil, J. C. Baraza, J. V. Busquets, Pedro J. Gil
    Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10418-10425 [Conf]
  14. J. Gracia, J. C. Baraza, Daniel Gil, Pedro J. Gil
    A Study of the Experimental Validation of Fault-Tolerant Systems Using Different VHDL-Based Fault Injection Techniques. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:140- [Conf]
  15. Daniel Gil, J. Gracia, J. C. Baraza, Pedro J. Gil
    A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:73-79 [Conf]
  16. José Carlos Campelo, Pedro Yuste, Francisco Rodríguez, Pedro J. Gil, Juan José Serrano
    Dependability Evaluation of Fault Tolerant Distributed Industrial Control Systems. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:384-388 [Conf]
  17. Pedro Yuste, Juan-Carlos Ruiz-Garcia, Lenin Lemus, Pedro J. Gil
    Non-intrusive Software-Implemented Fault Injection in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    LADC, 2003, pp:23-38 [Conf]
  18. J. Gracia, Daniel Gil, J. C. Baraza, Pedro J. Gil
    Using VHDL-Based Fault Injection to exercise Error Detection Mechanisms in the Time-Triggered Architecture. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:316-320 [Conf]
  19. Juan Carlos Ruiz, José Carlos Campelo, Pedro J. Gil, Juan Pardo
    On-chip Debugging-based Fault Emulation for Robustness Evaluation of Embedded Software Components. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:57-64 [Conf]
  20. José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings
    Adding instruction cache effect to schedulability analysis of preemptive real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 1996, pp:204-0 [Conf]
  21. José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings
    Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1996, pp:195-202 [Conf]
  22. José Carlos Campelo, Pedro Yuste, Francisco Rodríguez, Pedro J. Gil, Juan José Serrano
    Hierarchical Reliability and Safety Models of Fault Tolerant Distributed Industrial Control Systems. [Citation Graph (0, 0)][DBLP]
    SAFECOMP, 1999, pp:202-215 [Conf]
  23. Sara Blanc, Pedro J. Gil
    Improving the Multiple Errors Detection Coverage in Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SRDS, 2003, pp:303-0 [Conf]
  24. José Carlos Campelo, Francisco Rodríguez, Pedro J. Gil, Juan José Serrano
    Design and Validation of a Distributed Industrial Control System's Nodes. [Citation Graph (0, 0)][DBLP]
    Symposium on Reliable Distributed Systems, 1999, pp:300-301 [Conf]
  25. David de Andrés, Juan Carlos Ruiz, Daniel Gil, Pedro Gil
    Fast Emulation of Permanent Faults in VLSI Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  26. Daniel Gil, J. Gracia, J. C. Baraza, Pedro J. Gil
    Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:41-51 [Journal]

  27. Analysis of the influence of intermittent faults in a microcontroller. [Citation Graph (, )][DBLP]


  28. Temporal Characterization of Embedded Systems Using Nexus. [Citation Graph (, )][DBLP]


  29. Dependability Assessment for the Selection of Embedded Cores. [Citation Graph (, )][DBLP]


  30. Generic Design and Automatic Deployment of NMR Strategies on HW Cores. [Citation Graph (, )][DBLP]


  31. An Attack Injection Approach to Evaluate the Robustness of Ad Hoc Networks. [Citation Graph (, )][DBLP]


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