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Andrea Fedeli:
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Publications of Author
- Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud
Formal Verification Techniques: Industrial Status and Perspectives. [Citation Graph (0, 0)][DBLP] DATE, 2002, pp:1050-1051 [Conf]
- Giacomo Bucci, Andrea Fedeli, Luigi Sassoli, Enrico Vicario
Modeling Flexible Real Time Systems with Preemptive Time Petri Nets. [Citation Graph (0, 0)][DBLP] ECRTS, 2003, pp:279-286 [Conf]
- Paolo Azzoni, Andrea Fedeli, Franco Fummi, Graziano Pravadelli, Umberto Rossi, Franco Toto
An error simulation based approach to measure error coverage of formal properties. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2002, pp:53-58 [Conf]
- Giacomo Bucci, Andrea Fedeli, Enrico Vicario
Predicting Timeliness of Reactive Systems under Flexible Scheduling. [Citation Graph (0, 0)][DBLP] ISADS, 2003, pp:125-130 [Conf]
- Umberto Rossi, Andrea Fedeli, Marco Boschini, Franco Toto
Concrete Impact of Formal Verification on Quality in IP Design and Implementation. [Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:38-43 [Conf]
- Nicola Bombieri, Andrea Fedeli, Franco Fummi
Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling. [Citation Graph (0, 0)][DBLP] MEMOCODE, 2005, pp:239-240 [Conf]
- Franco Fummi, Graziano Pravadelli, Andrea Fedeli, Umberto Rossi, Franco Toto
On the Use of a High-Level Fault Model to Check Properties Incompleteness. [Citation Graph (0, 0)][DBLP] MEMOCODE, 2003, pp:145-152 [Conf]
- Nicola Bombieri, Andrea Fedeli, Franco Fummi
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. [Citation Graph (0, 0)][DBLP] MTV, 2005, pp:127-132 [Conf]
- Michele Borgatti, Andrea Fedeli, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Cristina Marconcini, Graziano Pravadelli
A Verification Methodology for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP] MTV, 2004, pp:85-90 [Conf]
- Giacomo Bucci, Andrea Fedeli, Enrico Vicario
Specification and Simulation of Real Time Concurrent Systems Using Standard SDL Tools. [Citation Graph (0, 0)][DBLP] SDL Forum, 2003, pp:203-217 [Conf]
- Andrea Fedeli, Franco Fummi, Graziano Pravadelli
Properties Incompleteness Evaluation by Functional Verification. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2007, v:56, n:4, pp:528-544 [Journal]
- Giacomo Bucci, Andrea Fedeli, Luigi Sassoli, Enrico Vicario
Timed State Space Analysis of Real-Time Preemptive Systems. [Citation Graph (0, 0)][DBLP] IEEE Trans. Software Eng., 2004, v:30, n:2, pp:97-111 [Journal]
- Ka Lok Man, Andrea Fedeli, Michele Mercaldi, Menouer Boubekeur, Michel P. Schellekens
SC2SCFL: Automated SystemC to SystemCFL Translation. [Citation Graph (0, 0)][DBLP] SAMOS, 2007, pp:34-45 [Conf]
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows. [Citation Graph (, )][DBLP]
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