The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Cristiana Bolchini: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Fault Analysis in Networks with Concurrent Error Detection Properties. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:957-958 [Conf]
  2. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Specification for Self-Checking Data-Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1278-1283 [Conf]
  3. Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli
    Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:204-211 [Conf]
  4. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A CMOS Fault Tolerant Architecture for Swith-Level Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:10-18 [Conf]
  5. Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto
    A model of soft error effects in generic IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:334-342 [Conf]
  6. Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Co-Design: The FIR Case Study. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:433-441 [Conf]
  7. Cristiana Bolchini, Luigi Pomante, Donatella Sciuto, Fabio Salice
    A Synthesis Methodology Aimed at Improving the Quality of TSC Devices. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:247-255 [Conf]
  8. Cristiana Bolchini, Fabio Salice
    A Software Methodology for Detecting Hardware Faults in VLIW Data Paths. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:170-175 [Conf]
  9. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Designing Self-Checking FPGAs through Error Detection Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:60-68 [Conf]
  10. Cristiana Bolchini, Donatella Sciuto, Fabio Salice
    Designing Networks with Error Detection Properties through the Fault-Error Relation. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:290-297 [Conf]
  11. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia
    An Integrated Design Approach for Self-Checking FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:443-450 [Conf]
  12. Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto
    Combined software and hardware techniques for the design of reliable IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:265-273 [Conf]
  13. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:32-0 [Conf]
  14. Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio
    SEU mitigation for sram-based fpgas through dynamic partial reconfiguration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:55-60 [Conf]
  15. Cristiana Bolchini, Donatella Sciuto, Fabio Salice
    A TSC Evaluation Function for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:555-560 [Conf]
  16. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    Reliability Properties Assessment at System Level: A Co-design Framework. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:165-171 [Conf]
  17. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:32-0 [Conf]
  18. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Designing Reliable Embedded Systems Based on 32 Bit Microprocessors. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:137- [Conf]
  19. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    CMOS Reliability Improvements Through a New Fault Tolerant Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:83-86 [Conf]
  20. Cristiana Bolchini, Franco Fummi, R. Gemelli, Fabio Salice
    A BDD Based Algorithm for Detecting Difficult Faults. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2015-2018 [Conf]
  21. Cristiana Bolchini, Franco Fummi, Donatella Sciuto
    Two-Dimensional Sequential Array Architectures: Design for Testability Approaches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:81-84 [Conf]
  22. Cristiana Bolchini, Donatella Sciuto
    An Output/State Encoding for Self-Checking Finite State Machine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2136-2139 [Conf]
  23. Cristiana Bolchini, William Fornaciari, Fabio Salice, Donatella Sciuto
    Concurrent Error Detection at Architectural Level. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:72-75 [Conf]
  24. Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto
    On-line fault detection in a hardware/software co-design environment. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:51-56 [Conf]
  25. Cristiana Bolchini, Carlo Curino, Fabio A. Schreiber, Letizia Tanca
    Context Integration for Mobile Data Tailoring. [Citation Graph (0, 0)][DBLP]
    MDM, 2006, pp:5- [Conf]
  26. Cristiana Bolchini, Elisa Quintarelli
    Context-Driven Data Filtering: A Methodology. [Citation Graph (0, 0)][DBLP]
    OTM Workshops (2), 2006, pp:1986-1995 [Conf]
  27. Cristiana Bolchini, Carlo Curino, Marco Giorgetta, Alessandro Giusti, Antonio Miele, Fabio A. Schreiber, Letizia Tanca
    PoLiDBMS: Design and Prototype Implementation of a DBMS for Portable Devices. [Citation Graph (0, 0)][DBLP]
    SEBD, 2004, pp:166-177 [Conf]
  28. Cristiana Bolchini, Carlo Curino, Fabio A. Schreiber, Letizia Tanca
    Context integration for mobile data tailoring. [Citation Graph (0, 0)][DBLP]
    SEBD, 2006, pp:48-55 [Conf]
  29. Cristiana Bolchini, Fabio Salice, Fabio A. Schreiber, Letizia Tanca
    Physical and Logical Data Structures for Very Small Databases. [Citation Graph (0, 0)][DBLP]
    SEBD, 2002, pp:337-344 [Conf]
  30. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A new switching-level approach to multiple-output functions synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:125-129 [Conf]
  31. Cristiana Bolchini, Fabio A. Schreiber
    Smart card embedded information systems: a methodology for privacy oriented architectural design. [Citation Graph (0, 0)][DBLP]
    Data Knowl. Eng., 2002, v:41, n:2-3, pp:159-182 [Journal]
  32. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
    Fault Analysis for Networks with Concurrent Error Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:66-74 [Journal]
  33. Cristiana Bolchini, Fabio A. Schreiber, Letizia Tanca
    A methodology for a Very Small Data Base design. [Citation Graph (0, 0)][DBLP]
    Inf. Syst., 2007, v:32, n:1, pp:61-82 [Journal]
  34. Cristiana Bolchini, Paolo Ferrandi, Pier Luca Lanzi, Fabio Salice
    Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:8-9, pp:516-533 [Journal]
  35. Cristiana Bolchini, Fred J. Meyer
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:237-238 [Journal]
  36. Cristiana Bolchini, Fabio A. Schreiber, Letizia Tanca
    A context-aware methodology for very small data base design. [Citation Graph (0, 0)][DBLP]
    SIGMOD Record, 2004, v:33, n:1, pp:71-76 [Journal]
  37. Cristiana Bolchini, Fabio Salice, Fabio A. Schreiber, Letizia Tanca
    Logical and physical design issues for smart card databases. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Inf. Syst., 2003, v:21, n:3, pp:254-285 [Journal]
  38. Cristiana Bolchini, Elisa Quintarelli, Rosalba Rossato, Letizia Tanca
    Using Context for the Extraction of Relational Views. [Citation Graph (0, 0)][DBLP]
    CONTEXT, 2007, pp:108-121 [Conf]
  39. Cristiana Bolchini, Elisa Quintarelli, Rosalba Rossato
    Relational Data Tailoring Through View Composition. [Citation Graph (0, 0)][DBLP]
    ER, 2007, pp:149-164 [Conf]
  40. Cristiana Bolchini, Paolo Ferrandi, Pier Luca Lanzi, Fabio Salice
    Toward an FPGA implementation of XCS. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:2053-2060 [Conf]
  41. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Specification for Self-Checking Data-Paths [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  42. Cristiana Bolchini
    A software methodology for detecting hardware faults in VLIW data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:458-468 [Journal]
  43. Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto
    Design of VHDL-based totally self-checking finite-state machine and data-path descriptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:98-103 [Journal]

  44. ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration. [Citation Graph (, )][DBLP]


  45. A novel methodology for designing TSC networks based on the parity bit code. [Citation Graph (, )][DBLP]


  46. A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip. [Citation Graph (, )][DBLP]


  47. TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs. [Citation Graph (, )][DBLP]


  48. Design Space Exploration for the Design of Reliable. [Citation Graph (, )][DBLP]


  49. A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems. [Citation Graph (, )][DBLP]


  50. An Incremental Approach to Functional Diagnosis. [Citation Graph (, )][DBLP]


  51. Fault Models and Injection Strategies in SystemC Specifications. [Citation Graph (, )][DBLP]


  52. Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  53. Multi-level fault modeling for transaction-level specifications. [Citation Graph (, )][DBLP]


  54. CADD: A Tool for Context Modeling and Data Tailoring. [Citation Graph (, )][DBLP]


  55. An integrated flow for the design of hardened circuits on SRAM-based FPGAs. [Citation Graph (, )][DBLP]


  56. And what can context do for data? [Citation Graph (, )][DBLP]


Search in 0.059secs, Finished in 0.062secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002