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Publications of Author

1. Gregorio Cappuccino, Giuseppe Cocorullo
   CMOS sizing rule for high performance long interconnects. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:817- [Conf]
   
2. Gregorio Cappuccino
   Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. [Citation Graph (0, 0)][DBLP]
   DSD, 2003, pp:138-143 [Conf]
   
3. Gregorio Cappuccino, Giuseppe Cocorullo
   A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines. [Citation Graph (0, 0)][DBLP]
   EUROMICRO, 1999, pp:1204-1208 [Conf]
   
4. Gregorio Cappuccino, Giuseppe Cocorullo
   Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2002, pp:438-447 [Conf]
   
5. Gregorio Cappuccino, Andrea Pugliese 0002, Giuseppe Cocorullo
   Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2005, pp:329-336 [Conf]
   
6. Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo
   A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2006, pp:311-318 [Conf]
   
7. Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo
   Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2006, pp:524-531 [Conf]
   
8. Andrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo
   Settling Time Minimization of Operational Amplifiers. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2007, pp:107-116 [Conf]
   
9. 
   Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers. [Citation Graph (, )][DBLP]