The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Yu-Tsun Chien: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
    Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:279-280 [Conf]
  2. Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen
    A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:528-531 [Conf]
  3. Chua-Chin Wang, Cheng-Fa Tsai, Yu-Tsun Chien
    Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2001, v:17, n:2, pp:313-324 [Journal]
  4. Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
    Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002