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Publications of Author

1. Francky Catthoor, Andrea Cuomo, Grant Martin, Patrick Groeneveld, Rudy Lauwereins, Karen Maex, Patrick van de Steeg, Ron Wilson
   How Can System-Level Design Solve the Interconnect Technology Scaling Problem? [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:332-339 [Conf]
   
2. Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
   Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:36-42 [Conf]
   
3. Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor, Karen Maex
   Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:914-919 [Conf]
   
4. Hasan Ymeri, Bart Nauwelaers, Karen Maex, David De Roest, Michele Stucchi, Servaas Vandenberghe
   Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:1113- [Conf]
   
5. Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene
   Statistically Aware SRAM Memory Array Design. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:25-30 [Conf]
   
6. Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex
   Interconnect width selection for deep submicron designs using the table lookup method. [Citation Graph (0, 0)][DBLP]
   SLIP, 2004, pp:41-44 [Conf]
   
7. Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex
   Impact of interconnect resistance increase on system performance of low power and high performance designs. [Citation Graph (0, 0)][DBLP]
   SLIP, 2006, pp:85-90 [Conf]
   
8. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
   Global interconnect trade-off for technology over memory modules to application level: case study. [Citation Graph (0, 0)][DBLP]
   SLIP, 2003, pp:125-132 [Conf]
   
9. Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex
   Interconnect exploration for future wire dominated technologies. [Citation Graph (0, 0)][DBLP]
   SLIP, 2002, pp:105-106 [Conf]
   
10. Hasan Ymeri, Bart Nauwelaers, Karen Maex
    Computation of capacitance matrix for integrated circuit interconnects using semi-analytic Green's function method. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:30, n:1, pp:55-63 [Journal]
    
11. Hasan Ymeri, Bart Nauwelaers, Karen Maex
    Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:30, n:2, pp:133-141 [Journal]
    
12. Hasan Ymeri, Bart Nauwelaers, Karen Maex, Servaas Vandenberghe, David De Roest
    A CAD-oriented analytical model for frequency-dependent series resistance and inductance of microstrip on-chip interconnect on silicon substrate. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:26, n:1, pp:45-48 [Journal]
    
13. Y.-L. Li, Zs. Tökei, Ph. Roussel, Guido Groeseneken, Karen Maex
    Layout dependency induced deviation from Poisson area scaling in BEOL dielectric reliability. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:9-11, pp:1299-1304 [Journal]
    
14. Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
    Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]