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Publications of Author

1. Jovanka Ciric, Gin Yee, Carl Sechen
   Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:277-282 [Conf]
   
2. Tyler Thorp, Gin Yee, Carl Sechen
   Domino logic synthesis using complex static gates. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:242-247 [Conf]
   
3. Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen
   Output Prediction Logic: A High-Performance CMOS Design Technique. [Citation Graph (0, 0)][DBLP]
   ICCD, 2000, pp:247-0 [Conf]
   
4. Tyler Thorp, Gin Yee, Carl Sechen
   Design and Synthesis of Monotonic Circuits. [Citation Graph (0, 0)][DBLP]
   ICCD, 1999, pp:569-572 [Conf]
   
5. Gin Yee, Carl Sechen
   Clock-Delayed Domino for Adder and Combinational Logic Desig. [Citation Graph (0, 0)][DBLP]
   ICCD, 1996, pp:332-0 [Conf]
   
6. Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen
   An Automated Shielding Algorithm and Tool For Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
   ISQED, 2000, pp:369-374 [Conf]
   
7. Gin Yee, Carl Sechen
   Clock-delayed domino for dynamic circuit design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:425-430 [Journal]
   
8. G. N. Hoyer, Gin Yee, Carl Sechen
   Locally clocked pipelines and dynamic logic. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:58-62 [Journal]