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Publications of Author

1. Ashutosh Chakraborty, Prassanna Sithambaram, K. Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
   Thermal resilient bounded-skew clock tree optimization methodology. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:832-837 [Conf]
   
2. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
   Dynamic thermal clock skew compensation using tunable delay buffers. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2006, pp:162-167 [Conf]
   
3. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
   Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2006, pp:214-224 [Conf]
   
4. Ashutosh Chakraborty, Enrico Macii, Massimo Poncino
   Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2005, pp:297-307 [Conf]
   
5. Pradeep Varma, Ashutosh Chakraborty
   Low-Voltage, Double-Edge-Triggered Flip Flop. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2003, pp:11-20 [Conf]
   
6. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
   Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
7. 
   An integrated nonlinear placement framework with congestion and porosity aware buffer planning. [Citation Graph (, )][DBLP]
   
   
8. 
   RegPlace: a high quality open-source placement framework for structured ASICs. [Citation Graph (, )][DBLP]
   
   
9. 
   Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. [Citation Graph (, )][DBLP]
   
   
10. 
    Analysis and optimization of NBTI induced clock skew in gated clock trees. [Citation Graph (, )][DBLP]
    
    
11. 
    PASAP: power aware structured ASIC placement. [Citation Graph (, )][DBLP]
    
    
12. 
    On stress aware active area sizing, gate sizing, and repeater insertion. [Citation Graph (, )][DBLP]
    
    
13. 
    Skew management of NBTI impacted gated clock trees. [Citation Graph (, )][DBLP]