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Prassanna Sithambaram: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Ashutosh Chakraborty, Prassanna Sithambaram, K. Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
Thermal resilient bounded-skew clock tree optimization methodology. [Citation Graph (0, 0)][DBLP]
DATE, 2006, pp:832-837 [Conf] - Prassanna Sithambaram, Alberto Macii, Enrico Macii
Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs. [Citation Graph (0, 0)][DBLP]
ACM Great Lakes Symposium on VLSI, 2005, pp:377-380 [Conf] - Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic thermal clock skew compensation using tunable delay buffers. [Citation Graph (0, 0)][DBLP]
ISLPED, 2006, pp:162-167 [Conf] - Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. [Citation Graph (0, 0)][DBLP]
PATMOS, 2006, pp:214-224 [Conf] - Prassanna Sithambaram, Alberto Macii, Enrico Macii
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs. [Citation Graph (0, 0)][DBLP]
PATMOS, 2005, pp:477-487 [Conf] - K. Duraisami, Prassanna Sithambaram, A. Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. [Citation Graph (0, 0)][DBLP]
ISCAS, 2007, pp:1061-1064 [Conf] - Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. [Citation Graph (0, 0)][DBLP]
ISCAS, 2006, pp:- [Conf] - Prassanna Sithambaram, Alberto Macii, Enrico Macii
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses. [Citation Graph (0, 0)][DBLP]
PATMOS, 2007, pp:232-241 [Conf]
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