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John Dielissen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mauro Cocco, John Dielissen, Marc J. M. Heijligers, Andries Hekstra, Jos Huisken
    A Scalable Architecture for LDPC Decodin. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:88-95 [Conf]
  2. John Dielissen, Andries Hekstra, Vincent Berg
    Low cost LDPC decoder for DVB-S2. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:130-135 [Conf]
  3. John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken, Albert van der Werf
    Power-efficient layered turbo decoder processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:246-251 [Conf]
  4. Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema
    A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1182-1187 [Conf]
  5. Andrei Radulescu, John Dielissen, Kees G. W. Goossens, Edwin Rijpkema, Paul Wielage
    An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:878-883 [Conf]
  6. Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander
    Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10350-10355 [Conf]
  7. Kees Goossens, John Dielissen, Andrei Radulescu
    Æthereal Network on Chip: Concepts, Architectures, and Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:414-421 [Journal]
  8. Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees G. W. Goossens
    An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:4-17 [Journal]
  9. John Dielissen, Andries Hekstra
    Non-fractional parallelism in LDPC decoder implementations. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:337-342 [Conf]

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