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Publications of Author

1. Mauro Cocco, John Dielissen, Marc J. M. Heijligers, Andries Hekstra, Jos Huisken
   A Scalable Architecture for LDPC Decodin. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:88-95 [Conf]
   
2. John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken, Albert van der Werf
   Power-efficient layered turbo decoder processor. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:246-251 [Conf]
   
3. Marc Quax, Jos Huisken, Jef L. van Meerbergen
   A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:230-235 [Conf]
   
4. Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal
   Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:117-122 [Conf]
   
5. Ramesh Chidambaram, Rene van Leuken, Marc Quax, Ingolf Held, Jos Huisken
   A multistandard FFT processor for wireless system-on-chip implementations. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
6. Lennart Yseboodt, Michael De Nil, Jos Huisken, Mladen Berekovic, Qin Zhao, Frank Bouwens, Jef L. van Meerbergen
   Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2007, pp:385-395 [Conf]
   
7. Jos Huisken
   Integrating VLIW Processors with a Network on Chip. [Citation Graph (0, 0)][DBLP]
   SAMOS, 2007, pp:2- [Conf]
   
8. Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen
   Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2006, pp:80-85 [Conf]
   
9. 
   The challenges of implementing fine-grained power gating. [Citation Graph (, )][DBLP]
   
   
10. 
    Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP. [Citation Graph (, )][DBLP]
    
    
11. 
    Automatic synthesis of near-threshold circuits with fine-grained performance tunability. [Citation Graph (, )][DBLP]