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Publications of Author

1. Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi
   An Interconnect Channel Design Methodology for High Performance Integrated Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1138-1143 [Conf]
   
2. Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit
   Heterogeneous Programmable Logic Block Architectures. [Citation Graph (0, 0)][DBLP]
   DATE, 2003, pp:11118-11119 [Conf]
   
3. Herman Schmit, Vikas Chandra
   FPGA switch block layout and evaluation. [Citation Graph (0, 0)][DBLP]
   FPGA, 2002, pp:11-18 [Conf]
   
4. Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi
   A power aware system level interconnect design methodology for latency-insensitive systems. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:275-282 [Conf]
   
5. Vikas Chandra, Gary D. Carpenter, Jeff Burns
   Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. [Citation Graph (0, 0)][DBLP]
   ICCD, 2003, pp:134-139 [Conf]
   
6. Vikas Chandra, Herman Schmit
   Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2002, pp:35-40 [Conf]
   
7. Vikas Chandra, Anthony Xu, Herman Schmit
   A low power approach to system level pipelined interconnect design. [Citation Graph (0, 0)][DBLP]
   SLIP, 2004, pp:45-52 [Conf]
   
8. Herman Schmit, Vikas Chandra
   Layout techniques for FPGA switch blocks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:96-105 [Journal]
   
9. 
   Impact of voltage scaling on nanoscale SRAM reliability. [Citation Graph (, )][DBLP]
   
   
10. 
    On the efficacy of write-assist techniques in low voltage nanoscale SRAMs. [Citation Graph (, )][DBLP]
    
    
11. 
    TIMBER: Time borrowing and error relaying for online timing error resilience. [Citation Graph (, )][DBLP]
    
    
12. 
    Analytical model for TDDB-based performance degradation in combinational logic. [Citation Graph (, )][DBLP]
    
    
13. 
    A black box method for stability analysis of arbitrary SRAM cell structures. [Citation Graph (, )][DBLP]
    
    
14. 
    Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS. [Citation Graph (, )][DBLP]
    
    
15. 
    Designing dependable multicore system with unreliable components. [Citation Graph (, )][DBLP]
    
    
16. 
    Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation. [Citation Graph (, )][DBLP]
    
    
17. 
    Robust Circuit Design: Challenges and Solutions. [Citation Graph (, )][DBLP]