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George A. Constantinides: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Heuristic datapath allocation for multiple wordlength systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:791-797 [Conf]
  2. George A. Constantinides
    Perturbation Analysis for Word-length Optimization. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:81-90 [Conf]
  3. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Multiple Precision for Resource Minimization. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:307-308 [Conf]
  4. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Optimum Wordlength Allocation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:219-228 [Conf]
  5. George A. Constantinides, Abunaser Miah, Nalin Sidahao
    Word-Length Optimization of Folded Polynomial Evaluation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:285-286 [Conf]
  6. Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
    A Novel 2D Filter Design Methodology for Heterogeneous Devices. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:13-22 [Conf]
  7. Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
    Migrating Functionality from ROMS to Embedded Multipliers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:287-288 [Conf]
  8. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Structured System Methodology for FPGA Based System-on-A-Chip Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:271-272 [Conf]
  9. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:275-276 [Conf]
  10. Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
    Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:138-148 [Conf]
  11. Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
    Yield enhancements of design-specific FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:93-100 [Conf]
  12. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    Exploration of heterogeneous reconfigurable architectures (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:268- [Conf]
  13. Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
    Heterogeneity Exploration for Multiple 2D Filter Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:263-268 [Conf]
  14. Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
    Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:200-208 [Conf]
  15. Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
    Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:409-414 [Conf]
  16. Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides
    Parameterized Logic Power Consumption Models for FPGA based Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:626-629 [Conf]
  17. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Multiple-Wordlength Resource Binding. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:646-655 [Conf]
  18. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:323-332 [Conf]
  19. Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
    Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:124-129 [Conf]
  20. Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
    Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:77-82 [Conf]
  21. Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides
    FPGA-Accelerated Reconstruction of Gene Regulatory Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:323-328 [Conf]
  22. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Reconfigurable Platform for Real-Time Embedded Video Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:606-615 [Conf]
  23. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Structured Methodology for System-on-an-FPGA Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1047-1051 [Conf]
  24. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    Multiple Restricted Multiplication. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:374-383 [Conf]
  25. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    Power and Area Optimization for Multiple Restricted Multiplication. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:112-117 [Conf]
  26. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:341-346 [Conf]
  27. Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung
    A novel 2D filter design methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:532-535 [Conf]
  28. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    Architectures for function evaluation on FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:804-807 [Conf]
  29. Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
    A heuristic approach for multiple restricted multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:692-695 [Conf]
  30. George A. Constantinides, Gerhard J. Woeginger
    The complexity of multiple wordlength assignment. [Citation Graph (0, 0)][DBLP]
    Appl. Math. Lett., 2002, v:15, n:2, pp:137-140 [Journal]
  31. Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
    Guest Editors' Introduction: Field Programmable Logic and Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1361-1362 [Journal]
  32. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Wordlength optimization for linear digital signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1432-1442 [Journal]
  33. Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides
    Accuracy-Guaranteed Bit-Width Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1990-2000 [Journal]
  34. George A. Constantinides
    Word-length optimization for differentiable nonlinear systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:26-43 [Journal]
  35. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Synthesis of saturation arithmetic architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:3, pp:334-354 [Journal]
  36. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Optimum and heuristic synthesis of multiple word-length architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:39-57 [Journal]
  37. Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
    Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  38. Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Leong
    FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  39. Su-Shin Ang, George A. Constantinides
    Dynamic Memory Sub-System for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  40. Jonathan A. Clarke, George A. Constantinides
    High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  41. Konstantinos Masselos, George A. Constantinides, Qiang Liu
    Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  42. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  43. Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung
    Fast word-level power models for synthesis of FPGA-based arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  44. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    On-Chip Communication in Run-Time Assembled Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:168-176 [Conf]
  45. Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:205-216 [Conf]
  46. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    Run-Time Integration of Reconfigurable Video Processing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1003-1016 [Journal]

  47. Automatic On-chip Memory Minimization for Data Reuse. [Citation Graph (, )][DBLP]


  48. A Hybrid Memory Sub-system for Video Coding Applications. [Citation Graph (, )][DBLP]


  49. More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control. [Citation Graph (, )][DBLP]


  50. On the feasibility of early routing capacitance estimation for FPGAs. [Citation Graph (, )][DBLP]


  51. A floating-point Extended Kalman Filter implementation for autonomous mobile robots. [Citation Graph (, )][DBLP]


  52. An FPGA-based implementation of the MINRES algorithm. [Citation Graph (, )][DBLP]


  53. Area estimation and optimisation of FPGA routing fabrics. [Citation Graph (, )][DBLP]


  54. Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. [Citation Graph (, )][DBLP]


  55. Optimising designs by combining model-based and pattern-based transformations. [Citation Graph (, )][DBLP]


  56. Glitch-aware output switching activity from word-level statistics. [Citation Graph (, )][DBLP]


  57. FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. [Citation Graph (, )][DBLP]


  58. A Parallel Hardware Architecture for Image Feature Detection. [Citation Graph (, )][DBLP]


  59. Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA. [Citation Graph (, )][DBLP]


  60. A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. [Citation Graph (, )][DBLP]


  61. Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator. [Citation Graph (, )][DBLP]


  62. Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. [Citation Graph (, )][DBLP]


  63. A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs. [Citation Graph (, )][DBLP]


  64. Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. [Citation Graph (, )][DBLP]


  65. Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA. [Citation Graph (, )][DBLP]


  66. Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. [Citation Graph (, )][DBLP]


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