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Come Rozon :
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Jason Coppens , Dhamin Al-Khalili , Come Rozon VHDL Modelling and Analysis of Fault Secure Systems. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:148-152 [Conf ] Dhamin Al-Khalili , Saman Adham , Come Rozon , Moazzem Hossain , D. Racz Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. [Citation Graph (0, 0)][DBLP ] DFT, 1998, pp:84-92 [Conf ] Donald B. Shaw , Dhamin Al-Khalili , Come Rozon Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2001, pp:531-536 [Conf ] Michael Ogbonna Esonu , Dhamin Al-Khalili , Come Rozon Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:1714-1717 [Conf ] Donald Shaw , Dhamin Al-Khalili , Come Rozon Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2001, pp:263-266 [Conf ] Come Rozon On the Use of VHDL as a Multi-Valued Logic Simulator. [Citation Graph (0, 0)][DBLP ] ISMVL, 1996, pp:110-0 [Conf ] Come Rozon , H. T. Mouftah Testability Analysis of CMOS Temary Circuits. [Citation Graph (0, 0)][DBLP ] ISMVL, 1991, pp:158-165 [Conf ] D. B. Gravel , Germain Drolet , Come Rozon Improved VLSI Design for Decoding Concatenated Codes Comprising an Irreducible Cyclic Code and a Reed-Solomon Code. [Citation Graph (0, 0)][DBLP ] Information Theory and Applications, 1995, pp:104-110 [Conf ] Hussam Al-Hertani , Dhamin Al-Khalili , Come Rozon Leakage power dissipation in UDSM logic gates. [Citation Graph (0, 0)][DBLP ] Circuits, Signals, and Systems, 2005, pp:132-136 [Conf ] Donald B. Shaw , Dhamin Al-Khalili , Come Rozon Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models. [Citation Graph (0, 0)][DBLP ] Integration, 2002, v:32, n:1-2, pp:77-97 [Journal ] Donald Shaw , Dhamin Al-Khalili , Come Rozon Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries. [Citation Graph (0, 0)][DBLP ] Integration, 2006, v:39, n:4, pp:382-406 [Journal ] Donald B. Shaw , Dhamin Al-Khalili , Come Rozon IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2003, v:52, n:10, pp:1285-1297 [Journal ] Accurate Total Static Leakage Current Estimation in Transistor Stacks. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.002secs