The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Lee-Sup Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sunho Chang, Jong-Sun Kim, Lee-Sup Kim
    A Memory Architecture with 4-Address Configurations for Video Signal Processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:746- [Conf]
  2. Chun-Ho Kim, Lee-Sup Kim
    Adaptive Selection of an Index in a Texture Cache. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:295-300 [Conf]
  3. Jaewan Bae, Donghyun Kim, Lee-Sup Kim
    An 11M-triangles/sec 3D graphics clipping engine for triangle primitives. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4570-4573 [Conf]
  4. Kyusik Chung, Lee-Sup Kim
    A PN triangle generation unit for fast and simple tessellation hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:728-731 [Conf]
  5. Kyusik Chung, Donghyun Kim, Lee-Sup Kim
    A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4546-4549 [Conf]
  6. Inho Lee, Joung-Youn Kim, Yeon-Ho Im, Yunseok Choi, Hyunchul Shin, Changyoung Han, Donghyun Kim, Hyoungjoon Park, Young-Il Seo, Kyusik Chung, Chang-Hyo Yu, Kanghyup Chun, Lee-Sup Kim
    A hardware-like high-level language based environment for 3D graphics architecture exploration. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:512-515 [Conf]
  7. Byung-Do Yang, Lee-Sup Kim
    A low power charge sharing ROM using dummy bit lines. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:377-380 [Conf]
  8. Chang-Hyo Yu, Lee-Sup Kim
    A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:724-727 [Conf]
  9. Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
    A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4574-4577 [Conf]
  10. Hyeon-Cheol Mo, Jong-Sun Kim, Lee-Sup Kim
    A high-speed pattern decoder in MPEG-4 padding block hardware accelerator. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:197-200 [Conf]
  11. Sunho Chang, Lee-Sup Kim
    Design trade-off in merged DRAM logic for video signal processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:267-270 [Conf]
  12. Youngjoon Kim, Lee-Sup Kim
    A low power carry select adder with reduced area. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:218-221 [Conf]
  13. Byung-Do Yang, Lee-Sup Kim
    A low power charge-recycling ROM architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:510-513 [Conf]
  14. Chang-Hyo Yu, Lee-Sup Kim
    An adaptive spatial filter for early depth test. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:137-140 [Conf]
  15. Kwang-Il Oh, Lee-Sup Kim
    A high performance low power dynamic PLA with conditional evaluation scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:881-884 [Conf]
  16. Byung-Do Yang, Lee-Sup Kim
    An error pattern ROM compression method for continuous data. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:845-848 [Conf]
  17. Donghyun Kim, Lee-Sup Kim
    Division-free rasterizer for perspective-correct texture filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:153-156 [Conf]
  18. Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim
    A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:461-464 [Conf]
  19. Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu
    A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:373-376 [Conf]
  20. Kwang-Il Oh, Lee-Sup Kim
    A clock delayed sleep mode domino logic for wide dynamic OR gate. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:176-179 [Conf]
  21. Bum-Sik Kim, Dae-Hyum Chung, Lee-Sup Kim
    A new 4-2 adder and booth selector for low power MAC unit. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:100-103 [Conf]
  22. Chang-Young Han, Yeon-Ho Im, Lee-Sup Kim
    Geometry engine architecture with early backface culling hardware. [Citation Graph (0, 0)][DBLP]
    Computers & Graphics, 2005, v:29, n:3, pp:415-425 [Journal]
  23. Jin-Aeon Lee, Lee-Sup Kim
    SPARP: a single pass antialiased rasterization processor. [Citation Graph (0, 0)][DBLP]
    Computers & Graphics, 2000, v:24, n:2, pp:233-243 [Journal]
  24. Donghyun Kim, Lee-Sup Kim
    An Efficient Fragment Processing Technique in A-Buffer Implementation. [Citation Graph (0, 0)][DBLP]
    IEICE Transactions, 2004, v:87, n:1, pp:258-269 [Journal]
  25. Joung-Youn Kim, Lee-Sup Kim
    An Efficient Memory Address Converter for Soc-based 3d Graphics System. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:861-876 [Journal]
  26. Lee-Sup Kim, Robert W. Dutton
    Modeling of the distributed gate RC effect in MOSFET's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1365-1367 [Journal]
  27. Sunho Chang, Bum-Sik Kim, Lee-Sup Kim
    A programmable 3.2-GOPS merged DRAM logic for video signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2000, v:10, n:6, pp:967-973 [Journal]
  28. Joung-Youn Kim, Lee-Sup Kim, Seung-Ho Hwang
    An advanced contrast enhancement using partially overlapped sub-block histogram equalization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2001, v:11, n:4, pp:475-484 [Journal]
  29. Chun-Ho Kim, Si-Mun Seong, Jin-Aeon Lee, Lee-Sup Kim
    Winscale: an image-scaling algorithm using an area pixel model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:6, pp:549-553 [Journal]
  30. Seung-Kwon Paek, Lee-Sup Kim
    A real-time wavelet vector quantization algorithm and its VLSI architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2000, v:10, n:3, pp:475-489 [Journal]
  31. Yeon-Ho Im, Chang-Young Han, Lee-Sup Kim
    A Method to Generate Soft Shadows Using a Layered Depth Image and Warping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Vis. Comput. Graph., 2005, v:11, n:3, pp:265-272 [Journal]
  32. Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
    A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:254-267 [Journal]
  33. Byung-Do Yang, Lee-Sup Kim
    A low-power ROM using single charge-sharing capacitor and hierarchical bit line. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:313-322 [Journal]
  34. Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim
    Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:765-768 [Conf]
  35. Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim
    A low power SoC bus with low-leakage and low-swing technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. Kyung-Soo Ha, Lee-Sup Kim
    Charge-pump reducing current mismatch in DLLs and PLLs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  37. Kyusik Chung, Chang-Hyo Yu, Lee-Sup Kim
    Vertex cache of programmable geometry processor for mobile multimedia application. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  38. Seunghyun Cho, Chang-Hyo Yu, Lee-Sup Kim
    An efficient texture cache for programmable vertex shaders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  39. Ju-Pyo Hong, Kyung-Soo Ha, Lee-Sup Kim
    A 0.18µm CMOS 10Gb/s 1: 4 DEMUX using replica-bias circuits for optical receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  40. Hyunchul Shin, Jin-Aeon Lee, Lee-Sup Kim
    A hardware cost minimized fast Phong shader. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:297-304 [Journal]
  41. Byung-Do Yang, Lee-Sup Kim
    A low-power charge-recycling ROM architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:590-600 [Journal]

  42. Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm. [Citation Graph (, )][DBLP]


  43. High speed serial interface for mobile LCD driver IC. [Citation Graph (, )][DBLP]


  44. Area-efficient pixel rasterization and texture coordinate interpolation. [Citation Graph (, )][DBLP]


  45. Shader-based tessellation to save memory bandwidth in a mobile multimedia processor. [Citation Graph (, )][DBLP]


Search in 0.007secs, Finished in 0.010secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002