Search the dblp DataBase

Publications of Author

1. Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He
   Clocktree RLC Extraction with Efficient Inductance Modeling. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:522-0 [Conf]
   
2. Norman Chang, Valery Kanevsky, O. Sam Nakagawa, Khalid Rahmat, Soo-Young Oh
   Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect. [Citation Graph (0, 0)][DBLP]
   ICCD, 1997, pp:720-725 [Conf]
   
3. Soo-Young Oh, Khalid Rahmat, O. Sam Nakagawa, J. Moll
   A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect. [Citation Graph (0, 0)][DBLP]
   ICCD, 1996, pp:320-325 [Conf]
   
4. Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie
   Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. [Citation Graph (0, 0)][DBLP]
   ISQED, 2001, pp:185-190 [Conf]
   
5. Shen Lin, Norman Chang, O. Sam Nakagawa
   Quick On-Chip Self- and Mutual-Inductance Screen. [Citation Graph (0, 0)][DBLP]
   ISQED, 2000, pp:513-0 [Conf]
   
6. Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, Sam Nakagawa
   Instruction Prediction for Step Power Reduction. [Citation Graph (0, 0)][DBLP]
   ISQED, 2001, pp:211-216 [Conf]
   
7. Zhiping Yu, Dan Yergeau, Robert W. Dutton, Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie
   Full Chip Thermal Simulation. [Citation Graph (0, 0)][DBLP]
   ISQED, 2000, pp:145-150 [Conf]
   
8. Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He
   Ramp Up/Down Functional Unit to Reduce Step Power. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:13-24 [Conf]
   
9. Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu
   Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:799-805 [Journal]