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Guy Bois: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Luc Charest, Michel Reid, El Mostapha Aboulhamid, Guy Bois
    A methodology for interfacing open source systemC with a third party software. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:16- [Conf]
  2. James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
    .NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:732-733 [Conf]
  3. D. Quinn, Bruno Lavigueur, Guy Bois, El Mostapha Aboulhamid
    A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:364-371 [Conf]
  4. Marc Bertola, Guy Bois
    A methodology for the design of AHB bus master wrappers. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:90-97 [Conf]
  5. Manoucher Shaditalab, Guy Bois, Mohamad Sawan
    Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:337-338 [Conf]
  6. Mohamed Nekili, Yvon Savaria, Guy Bois
    Design of Clock Distribution Networks in Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:95-102 [Conf]
  7. Mohamed H. Zaki, Sofiène Tahar, Guy Bois
    A practical approach for monitoring analog circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:330-335 [Conf]
  8. Mohamed Nekili, Yvon Savaria, Guy Bois
    A Fast Low-Power Driver for Long Interconnections in VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:343-346 [Conf]
  9. Mohamed Nekili, Yvon Savaria, Guy Bois
    Minimizing process-induced skew using delay tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:426-429 [Conf]
  10. B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois
    Development of a high performance TSPC library for implementation of large digital building blocks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:443-446 [Conf]
  11. Luc Charest, El Mostapha Aboulhamid, Guy Bois
    Using Design Patterns for Type Unification and Introspection in SystemC. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:45-50 [Conf]
  12. Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois
    A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:24-29 [Conf]
  13. S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron
    Automating Functional Coverage Analysis Based on an Executable Specification. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:228-234 [Conf]
  14. S. Regimbal, Yvon Savaria, Guy Bois
    Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:87-92 [Conf]
  15. James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
    ESys.Net: a new solution for embedded systems modeling and simulation. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:107-114 [Conf]
  16. Marc Bertola, Guy Bois
    Teaching Bus Architectures with a Basic, Hands-On SOC Platform. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:68-0 [Conf]
  17. Jean-Francois Thibeault, Mortimer Hubin, Francois Deslauriers, Patrick Samson, Guy Bois
    A Reprogrammable SoC Design for a Real-Time Control Application. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:73-74 [Conf]
  18. Jérôme Chevalier, Maxime de Nanclas, Luc Filion, Olivier Benny, Mathieu Rondonneau, Guy Bois, El Mostapha Aboulhamid
    A SystemC Refinement Methodology for Embedded Software. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:2, pp:148-158 [Journal]
  19. Guy Bois, Eduard Cerny
    Efficient generation of diagonal constraints for 2-D mask compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1119-1126 [Journal]
  20. L. Moss, Maxime de Nanclas, Luc Filion, S. Fontaine, Guy Bois, M. Aboulhamid
    Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:876-881 [Conf]
  21. Alena Tsikhanovich, F. Rousseau, El Mostapha Aboulhamid, Guy Bois
    Transaction Level Modeling in Hardware/Software System Design using .Net Framework. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:140-143 [Conf]
  22. Mohamed Nekili, Guy Bois, Yvon Savaria
    Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:161-174 [Journal]
  23. B. Bosi, Guy Bois, Yvon Savaria
    Reconfigurable pipelined 2-D convolvers for fast digital signal processing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:299-308 [Journal]

  24. Exploring ISS Abstractions for Embedded Software Design. [Citation Graph (, )][DBLP]

  25. Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs. [Citation Graph (, )][DBLP]

  26. Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. [Citation Graph (, )][DBLP]

  27. Qualitative Abstraction based Verification for Analog Circuits. [Citation Graph (, )][DBLP]

  28. Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology. [Citation Graph (, )][DBLP]

  29. SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. [Citation Graph (, )][DBLP]

  30. Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. [Citation Graph (, )][DBLP]

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