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Laung-Terng Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu
    At-Speed Logic BIST for IP Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:860-861 [Conf]
  2. Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
    On per-test fault diagnosis using the X-fault model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:633-640 [Conf]
  3. Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo
    At-Speed Logic BIST Architecture for Multi-Clock Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:475-478 [Conf]
  4. Zuhi Sun, Laung-Terng Wang
    Self-Testing of Embedded RAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:148-156 [Conf]
  5. Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai
    VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:916-925 [Conf]
  6. Laung-Terng Wang, Edward J. McCluskey
    Circuits for Pseudo-Exhaustive Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:25-37 [Conf]
  7. Laung-Terng Wang, Edward J. McCluskey
    A Hybrid Design of Maximum-Length Sequence Generators. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:38-47 [Conf]
  8. Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
    A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:58-65 [Conf]
  9. Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
    On Low-Capture-Power Test Generation for Scan Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:265-270 [Conf]
  10. Laung-Terng Wang, Edward J. McCluskey
    Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:367-370 [Journal]
  11. Laung-Terng Wang, Edward J. McCluskey
    Linear Feedback Shift Register Design Using Cyclic Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:10, pp:1302-1306 [Journal]
  12. Laung-Terng Wang, Edward J. McCluskey
    Hybrid designs generating maximum-length sequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:1, pp:91-99 [Journal]
  13. Laung-Terng Wang, Edward J. McCluskey
    Circuits for pseudoexhaustive test pattern generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1068-1080 [Journal]
  14. B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu
    At-Speed Logic BIST for IP Cores [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  15. Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja
    Efficient Test Set Modification for Capture Power Reduction. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:319-330 [Journal]

  16. Analysis of Resistive Bridging Defects in a Synchronizer. [Citation Graph (, )][DBLP]


  17. Logic BIST Architecture for System-Level Test and Diagnosis. [Citation Graph (, )][DBLP]


  18. On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. [Citation Graph (, )][DBLP]


  19. Analysis of Resistive Open Defects in a Synchronizer. [Citation Graph (, )][DBLP]


  20. Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. [Citation Graph (, )][DBLP]


  21. VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. [Citation Graph (, )][DBLP]


  22. Turbo1500: Core-Based Design for Test and Diagnosis. [Citation Graph (, )][DBLP]


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