Analysis of Resistive Bridging Defects in a Synchronizer. [Citation Graph (, )][DBLP]
Logic BIST Architecture for System-Level Test and Diagnosis. [Citation Graph (, )][DBLP]
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. [Citation Graph (, )][DBLP]
Analysis of Resistive Open Defects in a Synchronizer. [Citation Graph (, )][DBLP]
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. [Citation Graph (, )][DBLP]
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. [Citation Graph (, )][DBLP]
Turbo1500: Core-Based Design for Test and Diagnosis. [Citation Graph (, )][DBLP]
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