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H. Chao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu
    At-Speed Logic BIST for IP Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:860-861 [Conf]
  2. J. H. Chang, H. Chao, Kimming So
    Cache Design of a Sub-Micron CMOS System/370. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:208-213 [Conf]
  3. B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu
    At-Speed Logic BIST for IP Cores [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

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