The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Michele Favalli: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli
    Virtual Fault Simulation of Distributed IP-Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:99-0 [Conf]
  2. Michele Favalli, Marcello Dalpasso
    An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1122- [Conf]
  3. Michele Favalli, Cecilia Metra
    Optimization of error detecting codes for the detection of crosstalk originated errors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:290-296 [Conf]
  4. Michele Favalli, Cecilia Metra
    Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:612-619 [Conf]
  5. Michele Favalli, Cecilia Metra
    On the Design of Self-Checking Functional Units Based on Shannon Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:368-375 [Conf]
  6. Cecilia Metra, Michele Favalli, Bruno Riccò
    On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:763- [Conf]
  7. Cecilia Metra, Michele Favalli, Bruno Riccò
    Highly Testable and Compact 1-out-of-n Code Checker with Single Output. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:981-982 [Conf]
  8. Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli
    Self-Checking Scheme for the On-Line Testing of Power Supply Noise. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:832-836 [Conf]
  9. Michele Favalli
    "Victim Gate" Crosstalk Fault Model. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:191-199 [Conf]
  10. Michele Favalli
    Annotated Bit Flip Fault Model. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:366-376 [Conf]
  11. Michele Favalli, Cecilia Metra
    Low-level error recovery mechanism for self-checking sequential circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:234-242 [Conf]
  12. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:271-278 [Conf]
  13. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    A Highly Testable 1-out-of-3 CMOS Checker. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:279-286 [Conf]
  14. Cecilia Metra, Michele Favalli, Bruno Riccò
    CMOS Self Checking Circuits with Faulty Sequential Functional Block. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:133-141 [Conf]
  15. Cecilia Metra, Michele Favalli, Bruno Riccò
    Highly Testable and Compact 1-out-of-n CMOS Checkers. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:142-150 [Conf]
  16. Cecilia Metra, Michele Favalli, Bruno Riccò
    Compact and low power on-line self-testing voting scheme. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:137-147 [Conf]
  17. Cecilia Metra, Michele Favalli, Bruno Riccò
    Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:174-182 [Conf]
  18. Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
    Modeling of Broken Connections Faults in CMOS ICs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:159-164 [Conf]
  19. Michele Favalli, Cecilia Metra
    Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:100-105 [Conf]
  20. Michele Favalli, Luca Benini
    Analysis of glitch power dissipation in CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:123-128 [Conf]
  21. Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò
    Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:486-495 [Conf]
  22. Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
    Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:466-475 [Conf]
  23. Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
    Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:865-874 [Conf]
  24. Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
    CMOS Design for Improved IC Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:934- [Conf]
  25. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:948-957 [Conf]
  26. Cecilia Metra, Michele Favalli, Bruno Riccò
    On-Line Testing Scheme for Clock's Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:587-596 [Conf]
  27. Cecilia Metra, Michele Favalli, Bruno Riccò
    On-line detection of logic errors due to crosstalk, delay, and transient faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:524-533 [Conf]
  28. Marcello Dalpasso, Michele Favalli, Piero Olivo
    Test pattern generation for I/sub DDQ/: increasing test quality. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:304-309 [Conf]
  29. Cecilia Metra, Michele Favalli, Bruno Riccò
    Embedded two-rail checkers with on-line testing ability. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:145-150 [Conf]
  30. Cecilia Metra, Michele Favalli, Bruno Riccò
    Highly testable and compact single output comparator. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:210-215 [Conf]
  31. Michele Favalli, Cecilia Metra
    Online Testing Approach for Very Deep-Submicron ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:2, pp:16-23 [Journal]
  32. Cecilia Metra, Michele Favalli, Bruno Riccò
    Concurrent Checking of Clock Signal Correctness. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:42-48 [Journal]
  33. Michele Favalli
    Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:3, pp:348-352 [Journal]
  34. Cecilia Metra, Michele Favalli, Bruno Riccò
    Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:6, pp:560-574 [Journal]
  35. Marcello Dalpasso, Michele Favalli
    A method for increasing the IDDQ testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1186-1188 [Journal]
  36. Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò
    Fault simulation of parametric bridging faults in CMOS IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1403-1410 [Journal]
  37. Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò
    Aliasing in signature analysis testing with multiple input shift registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1344-1353 [Journal]
  38. Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò
    An analytical model for the aliasing probability in signature analysis testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1133-1144 [Journal]
  39. Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò
    Testability measures in pseudorandom testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:794-800 [Journal]
  40. Michele Favalli, Marcello Dalpasso
    Bridging fault modeling and simulation for deep submicron CMOS ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:941-953 [Journal]
  41. Michele Favalli, Marcello Dalpasso, Piero Olivo
    Modeling and simulation of broken connections in CMOS IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:808-814 [Journal]
  42. Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò
    Fault simulation of unconventional faults in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:677-682 [Journal]
  43. Michele Favalli, Piero Olivo, Bruno Riccò
    A novel critical path heuristic for fast fault grading. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:544-548 [Journal]
  44. Michele Favalli, Piero Olivo, Bruno Riccò
    A probabilistic fault model for `analog' faults in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1459-1462 [Journal]
  45. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:770-776 [Journal]
  46. Michele Favalli
    A fuzzy model for path delay fault detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:943-956 [Journal]
  47. Michele Favalli, Cecilia Metra
    Interactive presentation: Pulse propagation for the detection of small delay defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1295-1300 [Conf]
  48. Michele Favalli, Cecilia Metra
    TMR voting in the presence of crosstalk faults at the voter inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2004, v:53, n:3, pp:342-348 [Journal]
  49. Cecilia Metra, Luca Schiano, Michele Favalli
    Concurrent detection of power supply noise. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:469-475 [Journal]
  50. Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
    Analysis of resistive bridging fault detection in BiCMOS digital ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:342-355 [Journal]
  51. Michele Favalli, Cecilia Metra
    Sensing circuit for on-line detection of delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:130-133 [Journal]
  52. Michele Favalli, Cecilia Metra
    Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:392-396 [Journal]
  53. Alessandro Bogliolo, Michele Favalli, Maurizio Damiani
    Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:415-419 [Journal]
  54. Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò
    Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:1, pp:23-29 [Journal]

  55. Testing scheme for IC's clocks. [Citation Graph (, )][DBLP]


  56. High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations. [Citation Graph (, )][DBLP]


  57. Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth. [Citation Graph (, )][DBLP]


Search in 0.023secs, Finished in 0.027secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002