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Raoul Velazco :
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Ph. Cheynet , B. Nicolescu , Raoul Velazco , Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante System safety through automatic high-level code transformations: an experimental evaluation. [Citation Graph (0, 0)][DBLP ] DATE, 2001, pp:297-301 [Conf ] B. Nicolescu , Raoul Velazco Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:20057-20063 [Conf ] Lorena Anghel , Ernesto Sánchez , Matteo Sonza Reorda , Giovanni Squillero , Raoul Velazco Coupling Different Methodologies to Validate Obsolete Microprocessors. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:250-255 [Conf ] Lorena Anghel , Raoul Velazco , S. Saleh , S. Deswaertes , A. El Moucary Preliminary Validation of an Approach Dealing with Processor Obsolescence. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:493-0 [Conf ] B. Nicolescu , P. Peronnard , Raoul Velazco , Yvon Savaria Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:377-384 [Conf ] B. Nicolescu , Yvon Savaria , Raoul Velazco SIED: Software Implemented Error Detection. [Citation Graph (0, 0)][DBLP ] DFT, 2003, pp:589-596 [Conf ] Raoul Velazco , A. Corominas , P. Ferreyra Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied. [Citation Graph (0, 0)][DBLP ] DFT, 2002, pp:108-116 [Conf ] Raoul Velazco , Régis Leveugle , O. Calvo Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. [Citation Graph (0, 0)][DBLP ] DFT, 2001, pp:259-0 [Conf ] Jean-Denis Muller , Ph. Cheynet , Raoul Velazco Analysis and Improvement of Neural Network Robustness for On-Board Satellite Image Processing. [Citation Graph (0, 0)][DBLP ] ICANN, 1997, pp:1211-1216 [Conf ] Monica Alderighi , Fabio Casini , Sergio D'Angelo , F. Faure , M. Mancini , S. Pastore , Giacomo R. Sechi , Raoul Velazco Radiation test methodology for SRAM-based FPGAs by using THESIC. [Citation Graph (0, 0)][DBLP ] IOLTS, 2003, pp:162- [Conf ] F. Kaddour , S. Rezgui , Raoul Velazco , S. Rodriguez , J. R. De Mingo Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach. [Citation Graph (0, 0)][DBLP ] IOLTW, 2002, pp:195- [Conf ] Fernanda Gusmão de Lima , Luigi Carro , Raoul Velazco , Ricardo Augusto da Luz Reis Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller. [Citation Graph (0, 0)][DBLP ] IOLTW, 2002, pp:194- [Conf ] Gian-Carlo Cardarilli , F. Kaddour , A. Leandri , Marco Ottavi , Salvatore Pontarelli , Raoul Velazco Bit Flip Injection in Processor-Based Architectures: A Case Study. [Citation Graph (0, 0)][DBLP ] IOLTW, 2002, pp:117-0 [Conf ] B. Nicolescu , Yvon Savaria , Raoul Velazco Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. [Citation Graph (0, 0)][DBLP ] IOLTS, 2004, pp:233-238 [Conf ] B. Nicolescu , Raoul Velazco , Matteo Sonza Reorda Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study. [Citation Graph (0, 0)][DBLP ] IOLTW, 2001, pp:172-177 [Conf ] Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante , Ph. Cheynet , B. Nicolescu , Raoul Velazco Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. [Citation Graph (0, 0)][DBLP ] IOLTW, 2000, pp:17-0 [Conf ] Fabian Vargas , Alexandre M. Amory , Raoul Velazco Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL. [Citation Graph (0, 0)][DBLP ] IOLTW, 2000, pp:67-72 [Conf ] Raoul Velazco , R. Ecoffet , F. Faure How to Characterize the Problem of SEU in Processors and Representative Errors Observed on Flight. [Citation Graph (0, 0)][DBLP ] IOLTS, 2005, pp:303-308 [Conf ] Raoul Velazco , Lorena Anghel , S. Saleh A Methodology for Test Replacement Solutions of Obsolete Processors. [Citation Graph (0, 0)][DBLP ] IOLTS, 2003, pp:209-213 [Conf ] Raoul Velazco , S. Rezgui Transient Bitflip Injection in Microprocessor Embedded Applications. [Citation Graph (0, 0)][DBLP ] IOLTW, 2000, pp:80-0 [Conf ] C. Bellon , Raoul Velazco Hardware and Software Tools for Microprocessor Functional Test. [Citation Graph (0, 0)][DBLP ] ITC, 1984, pp:804-820 [Conf ] C. Bellon , Raoul Velazco , Haissam Ziade Analysis of Experimental Results on Functional Testing and Diagnosis of Complex Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1988, pp:64-72 [Conf ] Raoul Velazco , Haissam Ziade , E. Kolokithas A Microprocessor Test Approach Allowing Fault Localization. [Citation Graph (0, 0)][DBLP ] ITC, 1985, pp:737-743 [Conf ] Raoul Velazco , Ch. Godin , Ph. Cheynet , Santiago Torres-Alegre , Diego Andina , M. B. Gordon Study of Two ANN Digital Implementations of a Radar Detector Candidate to an On-Board Satellite Experiment. [Citation Graph (0, 0)][DBLP ] IWANN (2), 1999, pp:615-624 [Conf ] Jim Chung , N. Derhacobian , Jean Gasiot , Michael Nicolaidis , David Towne , R. Velazco Soft Errors and Tolerance for Soft Errors. [Citation Graph (0, 0)][DBLP ] VTS, 2001, pp:279-280 [Conf ] Haissam Ziade , Rafic A. Ayoubi , Raoul Velazco A Survey on Fault Injection Techniques. [Citation Graph (0, 0)][DBLP ] Int. Arab J. Inf. Technol., 2004, v:1, n:2, pp:171-186 [Journal ] P. Caspi , J. Piotrowski , Raoul Velazco An A Priori Approach to the Evaluation of Signature Analysis Efficiency. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1991, v:40, n:9, pp:1068-1071 [Journal ] Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection. [Citation Graph (, )][DBLP ] A generic platform for remote accelerated tests and high altitude SEU experiments on advanced ICs: Correlation with MUSCA SEP3 calculations. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.153secs