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Paul M. Rosinger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
    Minimizing test power in SRAM through reduction of pre-charge activity. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1159-1164 [Conf]
  2. Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger
    Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1372-1373 [Conf]
  3. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Rapid Generation of Thermal-Safe Test Schedules. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:840-845 [Conf]
  4. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Scan Architecture for Shift and Capture Cycle Power Reduction. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:129-137 [Conf]
  5. Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:544-551 [Conf]
  6. Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi
    Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:477-485 [Conf]
  7. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:474-479 [Conf]
  8. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Power constrained test scheduling using power profile manipulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:251-254 [Conf]
  9. Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger
    Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:281-286 [Conf]
  10. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2502-2512 [Journal]
  11. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Power profile manipulation: a new approach for reducing test application time under power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1217-1225 [Journal]
  12. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1142-1153 [Journal]
  13. Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi
    Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:323-335 [Journal]
  14. Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi
    Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1647-1652 [Conf]
  15. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Rapid Generation of Thermal-Safe Test Schedules [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  16. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
    Reducing Power Dissipation in SRAM during Test. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:271-280 [Journal]

  17. MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC. [Citation Graph (, )][DBLP]


  18. SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation. [Citation Graph (, )][DBLP]


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