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Luca Fanucci: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    ASIP design and synthesis for non linear filtering in image processing. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:233-238 [Conf]
  2. Luca Fanucci, A. Giambastiani, Francesco Iozzi, Corrado Marino, A. Rocchi
    Platform Based Design for Automotive Sensor Conditioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:186-191 [Conf]
  3. Luca Fanucci, Riccardo Locatelli, Esa Petri
    VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:182-189 [Conf]
  4. Pasquale Ciao, Giulio Colavolpe, Luca Fanucci
    A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:174-181 [Conf]
  5. M. De Marinis, Luca Fanucci, A. Giambastiani, Alessandro Renieri, A. Rocchi, Christian Rosadini, Claudio Sicilia, Daniele Sicilia
    Sensor Platform Design for Automotive Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:346-355 [Conf]
  6. Massimo Rovini, Nicola E. L'Insalata, Francesco Rossi, Luca Fanucci
    VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:202-209 [Conf]
  7. Sergio Saponara, Michele Cassiano, Stefano Marsi, Riccardo Coen, Luca Fanucci
    Cost-effective VLSI Design of Non Linear Image Processing Filters. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:322-329 [Conf]
  8. Massimo Rovini, Francesco Rossi, Pasquale Ciao, Nicola L'Insalat, Luca Fanucci
    Layered Decoding of Non-Layered LDPC Codes. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:537-544 [Conf]
  9. Gianluca Casarosa, Michele Apuzzo, Luca Fanucci, Bruno Sarti
    Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:338-345 [Conf]
  10. Francesco Rossi, Massimo Rovini, Luca Fanucci
    Design and Validation of Digital Channels for a Galileo Receiver Prototype. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:545-549 [Conf]
  11. Luca Fanucci, Sergio Saponara, Andrea Cenciotti
    IP Reuse VLSI Architecture for Low Complexity Fast Motion Estimation in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1417-1424 [Conf]
  12. Luca Fanucci, Lorenzo Bertini, Sergio Saponara
    Programmable and Low Power VLSI Architecture for Full Search Motion Estimation in Multimedia Communications. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (III), 2000, pp:1395-1398 [Conf]
  13. Luca Fanucci, G. D'Angelo, A. Monterastelli, M. Paparo, B. Neri
    Fully integrated low-noise-amplifier with high quality factor L-C filter for 1.8 GHz wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:462-465 [Conf]
  14. Luca Fanucci, R. Roncella, Roberto Saletti
    Non-linearity reduction technique for delay-locked delay-lines. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:430-433 [Conf]
  15. Armando Armaroli, Marcello Coppola, Mario Diaz-Nava, Luca Fanucci
    High Level Modeling and Simulation of a VDSL Modem in SystemC 2.0 - IPsim. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:175-180 [Conf]
  16. Fernando De Bernardinis, Luca Fanucci, T. Ramacciotti, Pierangelo Terreni
    A QoS Internet Protocol Scheduler on the IXP1200 Network Platform. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:394-399 [Conf]
  17. Sergio Saponara, Luca Fanucci, L. Serafini
    Low-Power FFT/IFFT VLSI Macro Cell for Scalable Broadband VDSL Modem. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:161-166 [Conf]
  18. Sergio Saponara, Luca Fanucci, Pierangelo Terreni
    Context-Aware Algorithmic/Architectural Solutions for Real-time Embedded Video Systems. [Citation Graph (0, 0)][DBLP]
    WISES, 2004, pp:79-90 [Conf]
  19. Luca Fanucci, Massimiliano Forliti, Pierangelo Terreni
    FAST: FFT ASIC automated synthesis. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:33, n:1-2, pp:23-37 [Journal]
  20. Luca Fanucci, Sergio Saponara, Lorenzo Bertini
    A parametric VLSI architecture for video motion estimation. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:79-100 [Journal]
  21. Luca Fanucci, Edoardo Letta, Riccardo De Gaudenzi, Filippo Giannetti, Marco Luise
    VLSI implementation of a CDMA blind adaptive interference-mitigating detector. [Citation Graph (0, 0)][DBLP]
    IEEE Journal on Selected Areas in Communications, 2001, v:19, n:2, pp:179-190 [Journal]
  22. Sergio Saponara, Esa Petri, Marco Tonarelli, Iacopo Del Corona, Luca Fanucci
    FPGA-based networking systems for high data-rate and reliable in-vehicle communications. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:480-485 [Conf]
  23. Torben Brack, M. Alles, T. Lehnigk-Emden, Frank Kienle, Norbert Wehn, Nicola E. L'Insalata, Francesco Rossi, Massimo Rovini, Luca Fanucci
    Low complexity LDPC code decoders for next generation standards. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:331-336 [Conf]
  24. F. D'Ascoli, Francesco Iozzi, Corrado Marino, M. Melani, Marco Tonarelli, Luca Fanucci, A. Giambastiani, A. Rocchi, M. De Marinis
    Low-g accelerometer fast prototyping for automotive applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:486-491 [Conf]
  25. Luca Fanucci, A. Giambastiani, Francesco Iozzi, Corrado Marino, A. Rocchi
    Platform Based Design for Automotive Sensor Conditioning [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  26. Sergio Saponara, Luca Fanucci
    VLSI design investigation for low-cost, low-power FFT/IFFT processing in advanced VDSL transceivers. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:2, pp:133-148 [Journal]

  27. Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. [Citation Graph (, )][DBLP]


  28. Hot Wire Anemometric MEMS Sensor for Water Flow Monitoring. [Citation Graph (, )][DBLP]


  29. A Programmable and Low-EMI Integrated Half-Bridge Driver in BCD Technology. [Citation Graph (, )][DBLP]


  30. Shock immunity enhancement via resonance damping in gyroscopes for automotive applications. [Citation Graph (, )][DBLP]


  31. An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability. [Citation Graph (, )][DBLP]


  32. A High-Voltage Low-Power DC-DC buck regulator for automotive applications. [Citation Graph (, )][DBLP]


  33. Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes. [Citation Graph (, )][DBLP]


  34. Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems. [Citation Graph (, )][DBLP]


  35. LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control. [Citation Graph (, )][DBLP]


  36. Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication. [Citation Graph (, )][DBLP]


  37. Design of a Distributed Embedded System for Domotic Applications. [Citation Graph (, )][DBLP]


  38. Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications. [Citation Graph (, )][DBLP]


  39. A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes. [Citation Graph (, )][DBLP]


  40. A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes. [Citation Graph (, )][DBLP]


  41. Game Console Controller Interface for People with Disability. [Citation Graph (, )][DBLP]


  42. VHDL-AMS Modelling and System Verification Flow. [Citation Graph (, )][DBLP]


  43. Implementation of message-passing algorithms for the acquisition of spreading codes. [Citation Graph (, )][DBLP]


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