The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Marcelino B. Santos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira
    A Probabilistic Method for the Computation of Testability of RTL Constructs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:176-181 [Conf]
  2. Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira
    RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10994-10999 [Conf]
  3. Marcelino B. Santos, João Paulo Teixeira
    Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:549-0 [Conf]
  4. José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira
    Probabilistic Testability Analysis and DFT Methods at RTL. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:216-217 [Conf]
  5. F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, I. M. Teixeira, João Paulo Teixeira
    Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:279-284 [Conf]
  6. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:295-300 [Conf]
  7. Antonio Casimiro, F. Conçalves, João Paulo Teixeira, Marcelino B. Santos
    On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:263-270 [Conf]
  8. Antonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:109-116 [Conf]
  9. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:216-224 [Conf]
  10. P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Realistic Fault Analysis of CMOS Analog Building Blocks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:311-318 [Conf]
  11. A. Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa
    Fault Simulation Using Partially Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:839-848 [Conf]
  12. A. Parreira, João Paulo Teixeira, Marcelino B. Santos
    FPGAs BIST Evaluation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:333-343 [Conf]
  13. Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Modeling and Simulation of Time Domain Faults in Digital Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:5-10 [Conf]
  14. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:164-165 [Conf]
  15. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:197-201 [Conf]
  16. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:281-286 [Conf]
  17. O. P. Dias, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Quality of Electronic Design: From Architectural Level to Test Coverage. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:197-0 [Conf]
  18. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:207-212 [Conf]
  19. M. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:720-728 [Conf]
  20. F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos, João Paulo Teixeira
    Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:620-628 [Conf]
  21. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:377-385 [Conf]
  22. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Defect-oriented test quality assessment using fault sampling and simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:35-42 [Conf]
  23. Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
    RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:814-823 [Conf]
  24. M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Physical DFT for High Coverage of Realistic Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:642-651 [Conf]
  25. Marcelino B. Santos, F. M. Gongalves, Isabel C. Teixeira, João Paulo Teixeira
    Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:326-332 [Conf]
  26. Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira
    Test preparation for high coverage of physical defects in CMOS digital ICs. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:330-337 [Conf]
  27. A. Parreira, João Paulo Teixeira, Marcelino B. Santos
    Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 2004, v:23, n:5, pp:- [Journal]
  28. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:167-172 [Conf]
  29. D. Barros Júnior, M. Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, J. P. Teixeira
    Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:349-363 [Journal]

  30. Programmable aging sensor for automotive safety-critical applications. [Citation Graph (, )][DBLP]


  31. Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. [Citation Graph (, )][DBLP]


  32. Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. [Citation Graph (, )][DBLP]


  33. Built-in aging monitoring for safety-critical applications. [Citation Graph (, )][DBLP]


  34. Controllability and observability in mixed signal cores. [Citation Graph (, )][DBLP]


  35. Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. [Citation Graph (, )][DBLP]


  36. Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization. [Citation Graph (, )][DBLP]


Search in 0.004secs, Finished in 0.005secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002