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Mirko Loghi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Franco Fummi, Mirko Loghi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
    Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:798-803 [Conf]
  2. Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon
    Analyzing On-Chip Communication in a MPSoC Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:752-757 [Conf]
  3. Mirko Loghi, Paolo Azzoni, Massimo Poncino
    Tag Overflow Buffering: An Energy-Efficient Cache Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:520-525 [Conf]
  4. Mirko Loghi, Massimo Poncino
    Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:508-513 [Conf]
  5. Franco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino
    ISS-centric modular HW/SW co-simulation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:31-36 [Conf]
  6. Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino
    Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:276-281 [Conf]
  7. Mirko Loghi, Massimo Poncino, Luca Benini
    Cycle-accurate power analysis for multiprocessor systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:410-406 [Conf]
  8. Olga Golubeva, Mirko Loghi, Massimo Poncino
    On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:489-492 [Conf]
  9. Mirko Loghi, Luca Benini, Massimo Poncino
    Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:393-396 [Conf]
  10. Mirko Loghi, Massimo Poncino, Luca Benini
    Synchronization-driven dynamic speed scaling for MPSoCs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:346-349 [Conf]
  11. Mirko Loghi, Tiziana Margaria, Graziano Pravadelli, Bernhard Steffen
    Dynamic and Formal Verification of Embedded Systems: A Comparative Survey. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:6, pp:585-611 [Journal]
  12. Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, Massimo Poncino
    Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:5, pp:606-621 [Journal]
  13. Mirko Loghi, Massimo Poncino, Luca Benini
    Cache coherence tradeoffs in shared-memory MPSoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:383-407 [Journal]
  14. Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii
    Architectural leakage-aware management of partitioned scratchpad memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1665-1670 [Conf]
  15. Mirko Loghi, Luca Benini, Massimo Poncino
    Power macromodeling of MPSoC message passing primitives. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal]

  16. Energy-optimal synchronization primitives for single-chip multi-processors. [Citation Graph (, )][DBLP]


  17. Aging effects of leakage optimizations for caches. [Citation Graph (, )][DBLP]


  18. Locality-driven architectural cache sub-banking for leakage energy reduction. [Citation Graph (, )][DBLP]


  19. Dynamic indexing: concurrent leakage and aging optimization for caches. [Citation Graph (, )][DBLP]


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