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George Theodoridis:
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Publications of Author
- Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:247-252 [Conf]
- Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:247-252 [Conf]
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP] FCCM, 2004, pp:275-276 [Conf]
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. [Citation Graph (0, 0)][DBLP] FPGA, 2004, pp:252- [Conf]
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP] FPL, 2004, pp:868-873 [Conf]
- Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP] IPDPS, 2005, pp:- [Conf]
- Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
An automated development framework for a RISC processor with reconfigurable instruction set extensions. [Citation Graph (0, 0)][DBLP] IPDPS, 2006, pp:- [Conf]
- Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A methodology for partitioning DSP applications in hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2005, pp:1206-1209 [Conf]
- George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis
An efficient probabilistic method for logic circuits using real delay gate model. [Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:286-289 [Conf]
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. [Citation Graph (0, 0)][DBLP] PATMOS, 2004, pp:652-661 [Conf]
- Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis
A Novel Constant-Time Fault-Secure Binary Counter. [Citation Graph (0, 0)][DBLP] PATMOS, 2004, pp:742-749 [Conf]
- George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. [Citation Graph (0, 0)][DBLP] PATMOS, 2000, pp:76-87 [Conf]
- Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. [Citation Graph (0, 0)][DBLP] PATMOS, 2000, pp:47-55 [Conf]
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
A Novel Data-Path for Accelerating DSP Kernels. [Citation Graph (0, 0)][DBLP] SAMOS, 2004, pp:363-372 [Conf]
- Athanasios Milidonis, Grigoris Dimitroulakos, Michalis D. Galanis, George Theodoridis, Constantinos E. Goutis, Francky Catthoor
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. [Citation Graph (0, 0)][DBLP] SCOPES, 2004, pp:122-136 [Conf]
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. [Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:877-893 [Journal]
- S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis
A fast and accurate delay dependent method for switching estimation of large combinational circuits. [Citation Graph (0, 0)][DBLP] Journal of Systems Architecture, 2002, v:48, n:4-5, pp:113-124 [Journal]
- Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
A high-performance data path for synthesizing DSP kernels. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1154-1162 [Journal]
- Athanasios Kakarountas, Haralambos Michail, Athanasios Milidonis, Costas E. Goutis, George Theodoridis
High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. [Citation Graph (0, 0)][DBLP] The Journal of Supercomputing, 2006, v:37, n:2, pp:179-195 [Journal]
- Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2007, v:31, n:1, pp:1-14 [Journal]
- Nikolaos D. Zervas, George Theodoridis, Dimitrios Soudris
Behavioral-level event-driven power management for DECT digital receivers. [Citation Graph (0, 0)][DBLP] Microelectronics Journal, 2005, v:36, n:2, pp:163-172 [Journal]
- Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
The ARISE Reconfigurable Instruction Set Extensions Framework. [Citation Graph (0, 0)][DBLP] ICSAMOS, 2007, pp:153-160 [Conf]
- Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. [Citation Graph (0, 0)][DBLP] ARC, 2006, pp:217-229 [Conf]
- Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms [Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal]
- Paris Kitsos, George Theodoridis, Odysseas G. Koufopavlou
An efficient reconfigurable multiplier architecture for Galois field GF(2m). [Citation Graph (0, 0)][DBLP] Microelectronics Journal, 2003, v:34, n:10, pp:975-980 [Journal]
- Athanasios Kakarountas, Nikolaos D. Zervas, George Theodoridis, Haralambos Michail, Dimitrios Soudris
Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. [Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2006, v:2, n:3, pp:356-364 [Journal]
ARISE Machines: Extending Processors with Hybrid Accelerators. [Citation Graph (, )][DBLP]
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