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Nihar R. Mahapatra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kaushal R. Gandhi, Nihar R. Mahapatra
    Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1001-1006 [Conf]
  2. Krishnan Sundaresan, Nihar R. Mahapatra
    Value-based bit ordering for energy optimization of on-chip global signal buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:624-625 [Conf]
  3. Srivathsan Krishnamohan, Nihar R. Mahapatra
    Combining Error Masking and Error Detection Plus Recovery to Combat Soft Errors in Static CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DSN, 2005, pp:40-49 [Conf]
  4. Shantanu Dutt, Nihar R. Mahapatra
    Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:320-329 [Conf]
  5. Nihar R. Mahapatra, Shantanu Dutt
    Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:272-281 [Conf]
  6. Nihar R. Mahapatra, Shantanu Dutt
    Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1999, pp:122-129 [Conf]
  7. Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
    Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:111-114 [Conf]
  8. Srivathsan Krishnamohan, Nihar R. Mahapatra
    Analysis and design of soft-error hardened latches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:328-331 [Conf]
  9. Srivathsan Krishnamohan, Nihar R. Mahapatra
    An analysis of the robustness of CMOS delay elements. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:412-415 [Conf]
  10. Srivathsan Krishnamohan, Nihar R. Mahapatra
    Increasing the energy efficiency of pipelined circuits via slack redistribution. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:436-441 [Conf]
  11. Krishnan Sundaresan, Nihar R. Mahapatra
    Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:51-60 [Conf]
  12. Nihar R. Mahapatra, Douglas E. Covelli, Yuval Beres
    A Quantitative Evaluation of Limited-Memory Branch-and-Bound Algorithms. [Citation Graph (0, 0)][DBLP]
    IC-AI, 1999, pp:84-90 [Conf]
  13. Kaushal R. Gandhi, Nihar R. Mahapatra
    A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:426-0 [Conf]
  14. Srivathsan Krishnamohan, Nihar R. Mahapatra
    A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:126-131 [Conf]
  15. Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
    Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:458-463 [Conf]
  16. Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan
    Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:234-239 [Conf]
  17. Shantanu Dutt, Nihar R. Mahapatra
    Parallel A* Algorithms and Their Performance on Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:797-803 [Conf]
  18. Nihar R. Mahapatra, Shantanu Dutt
    Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:881-885 [Conf]
  19. Nihar R. Mahapatra, Shantanu Dutt
    Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:796-800 [Conf]
  20. Jiangjiang Liu, Nihar R. Mahapatra, Krishnan Sundaresan
    Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:220-221 [Conf]
  21. Krishnan Sundaresan, Nihar R. Mahapatra
    Code Compression Techniques for Embedded Systems and Their Effectiveness. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:262-263 [Conf]
  22. Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan
    The performance advantage of applying compression to the memory system. [Citation Graph (0, 0)][DBLP]
    MSP/ISMM, 2002, pp:86-96 [Conf]
  23. Nihar R. Mahapatra, Shantanu Dutt
    Scalable Duplicate Pruning Strategies for Parallel A* Graph Search. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:290-297 [Conf]
  24. Kaushal R. Gandhi, Nihar R. Mahapatra
    Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:570-575 [Conf]
  25. Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
    Energy-Efficient Compressed Address Transmission. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:592-597 [Conf]
  26. Krishnan Sundaresan, Nihar R. Mahapatra
    An Accurate Energy and Thermal Model for Global Signal Buses. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:685-690 [Conf]
  27. Sharath Jayaprakash, Nihar R. Mahapatra
    Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:127-134 [Conf]
  28. Nihar R. Mahapatra, Shantanu Dutt
    Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2000, v:11, n:2, pp:231-246 [Journal]
  29. Shantanu Dutt, Nihar R. Mahapatra
    Scalable Load Balancing Strategies for Parallel A* Algorithms. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:22, n:3, pp:488-505 [Journal]
  30. Nihar R. Mahapatra, Shantanu Dutt
    Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2001, v:61, n:10, pp:1391-1411 [Journal]
  31. Nihar R. Mahapatra, Shantanu Dutt
    Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2004, v:30, n:5-6, pp:867-881 [Journal]
  32. Shantanu Dutt, Nihar R. Mahapatra
    Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:9, pp:997-1015 [Journal]
  33. Nihar R. Mahapatra, Shantanu Dutt
    Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:7, pp:738-756 [Journal]
  34. Krishnan Sundaresan, Nihar R. Mahapatra
    An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:515-520 [Conf]
  35. Nihar R. Mahapatra, Shantanu Dutt
    An efficient delay-optimal distributed termination detection algorithm. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2007, v:67, n:10, pp:1047-1066 [Journal]

  36. Enhancing Available-Memory Cost-Bounded Iterative-Deepening Search. [Citation Graph (, )][DBLP]


  37. Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. [Citation Graph (, )][DBLP]


  38. An Instance-Based Learning Approach for Available-Memory Non-minimal Cost-Bounded Search. [Citation Graph (, )][DBLP]


  39. Dynamic User-Driven Available-Memory Non-Minimal Cost-Bounded Search. [Citation Graph (, )][DBLP]


  40. Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. [Citation Graph (, )][DBLP]


  41. Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass. [Citation Graph (, )][DBLP]


  42. Energy-optimal signaling and ordering of bits for area-constrained interconnects. [Citation Graph (, )][DBLP]


  43. The role of interconnects in the performance scalability of multicore architectures. [Citation Graph (, )][DBLP]


  44. Partitioned reuse cache for energy-efficient soft-error protection of functional units. [Citation Graph (, )][DBLP]


  45. Slack redistribution in pipelined circuits for enhanced soft-error rate reduction. [Citation Graph (, )][DBLP]


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