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Anup Gangwar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
    Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:730-735 [Conf]
  2. Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee
    SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:273- [Conf]
  3. M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
    A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:2-7 [Conf]
  4. Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar
    SoC Synthesis with Automatic Hardware Software Interface Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:585-0 [Conf]
  5. Anup Gangwar, M. Balakrishnan, Anshul Kumar
    Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]

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