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Juan A. Montiel-Nelson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Bootstrapped full--swing CMOS driver for low supply voltage operation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:410-411 [Conf]
  2. José C. García, Juan A. Montiel-Nelson, J. Sosa, Héctor Navarro
    A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:680-681 [Conf]
  3. Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez
    A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:947-948 [Conf]
  4. Juan A. Montiel-Nelson, Saeid Nooshabadi, V. de Armas, Roberto Sarmiento, Antonio Núñez
    High Speed GaAs Subsystem Design using Feed Through Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:509-0 [Conf]
  5. Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, J. Sosa
    A Single Phase Latch for High Speed GaAs Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:760- [Conf]
  6. R. Morales-Ramos, Juan A. Montiel-Nelson, R. Berenguer, A. Garcia-Alonso
    Voltage Sensors for Supply Capacitor in Passive UHF RFID Transponders. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:625-629 [Conf]
  7. J. Sosa, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Efficient computation of the area/power consumption versus delay tradeoff curve for circuit critical path optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:527-530 [Conf]
  8. Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi
    A compact layout technique to minimize high frequency switching effects in high speed circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:96-99 [Conf]
  9. Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez
    A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:223-0 [Conf]
  10. J. Sosa, Juan A. Montiel-Nelson, Héctor Navarro, José C. García
    Functional Vector Generation for Combinational Circuits Based on Data Path Coverage Metric and Mixed Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:217-222 [Conf]
  11. Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi
    An Asynchronous Morphological Processor for Multi-Media Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:336-341 [Conf]
  12. Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri
    Micropipeline Architecture for Multiplier-less FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:451-456 [Conf]
  13. José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:881-884 [Conf]
  14. R. Morales-Ramos, J. Sosa, Juan A. Montiel-Nelson, A. Zwick, X. P. Nguyen
    Movement recognition and strain lecture algorithm for fracture monitoring system. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  15. R. Morales-Ramos, Juan A. Montiel-Nelson, H. Milosiu, R. Berenguer, A. Garcia-Alonso
    Adjustable Voltage Sensors for Power Supply Chains in Passive UHF RFID Transponders. [Citation Graph (0, 0)][DBLP]
    ETFA, 2006, pp:286-291 [Conf]
  16. Roberto Sarmiento, V. de Armas, José Francisco López, Juan A. Montiel-Nelson, Antonio Núñez
    A CORDIC processor for FFT computation and its implementation using gallium arsenide technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:18-30 [Journal]
  17. Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:300-307 [Journal]

  18. High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic. [Citation Graph (, )][DBLP]


  19. Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications. [Citation Graph (, )][DBLP]


  20. High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output. [Citation Graph (, )][DBLP]


  21. A geometric approach to register transfer level satisfiability. [Citation Graph (, )][DBLP]


  22. Low Power Bootstrapped CMOS Differential Cross Coupled Driver. [Citation Graph (, )][DBLP]


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