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Publications of Author

1. José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi
   Bootstrapped full--swing CMOS driver for low supply voltage operation. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:410-411 [Conf]
   
2. Juan A. Montiel-Nelson, Saeid Nooshabadi, V. de Armas, Roberto Sarmiento, Antonio Núñez
   High Speed GaAs Subsystem Design using Feed Through Logic. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:509-0 [Conf]
   
3. Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, J. Sosa
   A Single Phase Latch for High Speed GaAs Domino Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:760- [Conf]
   
4. Michael Dyer, David S. Taubman, Saeid Nooshabadi
   Improved throughput arithmetic coder for jpeg2000. [Citation Graph (0, 0)][DBLP]
   ICIP, 2004, pp:2817-2820 [Conf]
   
5. K. Oteng-Amoako, Saeid Nooshabadi, J. Yuan
   Design and Performance of Asymmetric Turbo Coded Hybrid-ARQ. [Citation Graph (0, 0)][DBLP]
   ICT, 2004, pp:1369-1381 [Conf]
   
6. Michael Dyer, David Taubman, Saeid Nooshabadi
   Reduced latency arithmetic decoder for JPEG2000 block decoding. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2005, pp:2076-2079 [Conf]
   
7. Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubman
   Efficient VLSI architecture for buffer used in EBCOT of JPEG2000 encoder. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:4361-4364 [Conf]
   
8. Amit Kumar Gupta, Saeid Nooshabadi, David S. Taubman
   Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:4373-4376 [Conf]
   
9. A. Pouladi, Saeid Nooshabadi
   Opcode encoding for low power embedded systems. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:5262-5265 [Conf]
   
10. Saeid Nooshabadi
    Modelling of effects of temperature profile in the MOS transistor characteristics. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:81-84 [Conf]
    
11. J. Sosa, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Efficient computation of the area/power consumption versus delay tradeoff curve for circuit critical path optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:527-530 [Conf]
    
12. Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi
    A compact layout technique to minimize high frequency switching effects in high speed circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:96-99 [Conf]
    
13. Kamran Eshraghian, Juan A. Montiel-Nelson, Saeid Nooshabadi
    An Asynchronous Morphological Processor for Multi-Media Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:336-341 [Conf]
    
14. Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri
    Micropipeline Architecture for Multiplier-less FIR Filters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:451-456 [Conf]
    
15. Saeid Nooshabadi, G. S. Visweswaran, D. Nagchoudhuri
    Current Mode Ternary D/A Converter. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:244-248 [Conf]
    
16. A. K. Gupta, Saeid Nooshabadi, David Taubman, Michael Dyer
    Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:7, pp:843-858 [Journal]
    
17. Amit Kumar Gupta, Saeid Nooshabadi, David Taubman
    Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 Encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1365-1368 [Conf]
    
18. José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:881-884 [Conf]
    
19. F. Sobhanmanesh, Saeid Nooshabadi
    VLSI architecture for 4×4 16-QAM V-BLAST decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
20. Chul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian
    3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:71-86 [Conf]
    
21. Victor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:300-307 [Journal]
    
22. 
    High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic. [Citation Graph (, )][DBLP]
    
    
23. 
    Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications. [Citation Graph (, )][DBLP]
    
    
24. 
    High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output. [Citation Graph (, )][DBLP]
    
    
25. 
    Analysis of Multiple Parallel Block Coding in JPEG2000. [Citation Graph (, )][DBLP]
    
    
26. 
    Error resilient JPEG2000 decoding for wireless applications. [Citation Graph (, )][DBLP]
    
    
27. 
    A feasible VLSI engine for soft-input-soft-output for joint source channel codes. [Citation Graph (, )][DBLP]
    
    
28. 
    An optimization strategy for low energy and high performance for the on-chip interconnect signalling. [Citation Graph (, )][DBLP]
    
    
29. 
    A geometric approach to register transfer level satisfiability. [Citation Graph (, )][DBLP]
    
    
30. 
    Low Power Bootstrapped CMOS Differential Cross Coupled Driver. [Citation Graph (, )][DBLP]