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Joachim Gerlach: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Joachim Gerlach, Wolfgang Rosenstiel
    A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:226-0 [Conf]
  2. Djones Lettnin, Axel G. Braun, Martin Bogdan, Joachim Gerlach, Wolfgang Rosenstiel
    Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:248-255 [Conf]
  3. Jan-Hendrik Oetjens, Joachim Gerlach, Wolfgang Rosenstiel
    Flexible specification and application of rule-based transformations in an automotive design flow. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:82-87 [Conf]
  4. Jürgen Ruf, Dirk W. Hoffmann, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Wolfgang Müller 0003
    The simulation semantics of systemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:64-70 [Conf]
  5. Thorsten Schubert, Jürgen Hanisch, Joachim Gerlach, Jens-E. Appell, Wolfgang Nebel
    Evaluation of a Refinement-Driven SystemC'-Based Design Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:262-267 [Conf]
  6. Heinz-Josef Eikerling, Wolfram Hardt, Joachim Gerlach, Wolfgang Rosenstiel
    A Methodology for Rapid Analysis and Optimization of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ECBS, 1996, pp:252-259 [Conf]
  7. Joachim Gerlach, Wolfgang Rosenstiel
    A Methodology and Tool for Automated Transformational High-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:545-548 [Conf]
  8. Djones Lettnin, Markus Winterholer, Axel G. Braun, Joachim Gerlach, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel
    Coverage Driven Verification applied to Embedded Software. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:159-164 [Conf]
  9. Axel G. Braun, Jan B. Freuer, Joachim Gerlach, Wolfgang Rosenstiel
    Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:55-0 [Conf]
  10. Robert Lissel, Joachim Gerlach, Robert Bosch GmbH
    Introducing new verification methods into a company's design flow: an industrial user's point of view. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:689-694 [Conf]

  11. On the Verification of High-Order Constraint Compliance in IC Design. [Citation Graph (, )][DBLP]

  12. Semiformal verification of temporal properties in automotive hardware dependent software. [Citation Graph (, )][DBLP]

  13. An automated flow for integrating hardware IP into the automotive systems engineering process. [Citation Graph (, )][DBLP]

  14. Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation. [Citation Graph (, )][DBLP]

  15. Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited). [Citation Graph (, )][DBLP]

  16. Industrial Partners Expectations from the ICODES Methodology. [Citation Graph (, )][DBLP]

  17. SystemC-Based Communication and Performance Analysis. [Citation Graph (, )][DBLP]

  18. Case Study: SystemC-Based Design of an Industrial Exposure Control Unit1. [Citation Graph (, )][DBLP]

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