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Publications of Author

1. Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III
   Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:656-663 [Conf]
   
2. Justin E. Harlow III, Franc Brglez
   Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. [Citation Graph (0, 0)][DBLP]
   FMCAD, 1998, pp:64-81 [Conf]
   
3. Justin E. Harlow III, Franc Brglez
   Design of experiments in BDD variable ordering: lessons learned. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:646-652 [Conf]
   
4. Justin E. Harlow III, Franc Brglez
   Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 1999, pp:452-455 [Conf]
   
5. V. Mahalingam, N. Ranganathan, Justin E. Harlow III
   A novel approach for variation aware power minimization during gate sizing. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2006, pp:174-179 [Conf]
   
6. Justin E. Harlow III
   Toward Design Technology in 2020: Trends, Issues, and Challenges. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2003, pp:3-4 [Conf]
   
7. Scott Davidson, Justin E. Harlow III
   Guest Editors' Introduction: Benchmarking for Design and Test. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:3, pp:12-14 [Journal]
   
8. Justin E. Harlow III
   Overview of Popular Benchmark Sets. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:3, pp:15-17 [Journal]
   
9. Justin E. Harlow III, Franc Brglez
   Design of experiments and evaluation of BDD ordering heuristics. [Citation Graph (0, 0)][DBLP]
   STTT, 2001, v:3, n:2, pp:193-206 [Journal]
   
10. 
    Architectures for Silicon Nanoelectronics and Beyond. [Citation Graph (, )][DBLP]