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Sezer Gören: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sezer Gören, F. Joel Ferguson
    CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:248-254 [Conf]
  2. Pak K. Chan, Mark J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu
    Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:308-309 [Conf]
  3. Sezer Gören, F. Joel Ferguson
    Testing Finite State Machines Based on a Structural Coverage Metric . [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:773-780 [Conf]
  4. Sezer Gören, F. Joel Ferguson
    Checking sequence generation for asynchronous sequential elements. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:406-413 [Conf]
  5. H. Fatih Ugurdag, Yahya Sahin, Onur Baskirt
    Population-Based FPGA Solution to Mastermind Game. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:237-246 [Conf]
  6. Sezer Gören, F. Joel Ferguson
    Test sequence generation for controller verification and test with high coverage. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:4, pp:916-938 [Journal]
  7. Sezer Gören, F. Joel Ferguson
    On state reduction of incompletely specified finite state machines. [Citation Graph (0, 0)][DBLP]
    Computers & Electrical Engineering, 2007, v:33, n:1, pp:58-69 [Journal]

  8. Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization. [Citation Graph (, )][DBLP]


  9. FPGA design security with time division multiplexed PUFs. [Citation Graph (, )][DBLP]


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