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Publications of Author

1. Matthew W. Heath, Wayne P. Burleson, Ian G. Harris
   Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:410-415 [Conf]
   
2. Andrés D. García, Jean-Luc Danger, Wayne P. Burleson
   Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. [Citation Graph (0, 0)][DBLP]
   FPGA, 2000, pp:220- [Conf]
   
3. Andrés D. García, Wayne P. Burleson, Jean-Luc Danger
   Power Modelling in Field Programmable Gate Arrays (FPGA). [Citation Graph (0, 0)][DBLP]
   FPL, 1999, pp:396-404 [Conf]
   
4. Mircea R. Stan, Wayne P. Burleson
   Coding a terminated bus for low power. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1995, pp:70-73 [Conf]
   
5. Mircea R. Stan, Wayne P. Burleson
   Two dimensional codes for low power. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1996, pp:335-340 [Conf]
   
6. Wayne P. Buleson, Louis L. Scharf
   Input/Output Design for VLSI Array Architectures. [Citation Graph (0, 0)][DBLP]
   VLSI, 1991, pp:357-366 [Conf]
   
7. Matthew W. Heath, Wayne P. Burleson, Ian G. Harris
   Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:12, pp:1532-1546 [Journal]
   
8. Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson
   Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:50-62 [Journal]
   
9. Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson
   An energy-aware active smart card. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1190-1199 [Journal]
   
10. Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson
    A reconfigurable, power-efficient adaptive Viterbi decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:4, pp:484-488 [Journal]
    
11. Bongjin Jung, Wayne P. Burleson
    Performance optimization of wireless local area networks through VLSI data compression. [Citation Graph (0, 0)][DBLP]
    Wireless Networks, 1998, v:4, n:1, pp:27-39 [Journal]
    
12. Romain Vaslin, Guy Gogniat, Eduardo Wanderley Neto, Russell Tessier, Wayne P. Burleson
    Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:146-153 [Conf]
    
13. Sheng Xu, Ibis Benito, Wayne P. Burleson
    Thermal Impacts on NoC Interconnects. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:220- [Conf]
    
14. Mircea R. Stan, Wayne P. Burleson
    Bus-invert coding for low-power I/O. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:49-58 [Journal]
    
15. Yongjin Jeong, Wayne P. Burleson
    VLSI array algorithms and architectures for RSA modular multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:211-217 [Journal]
    
16. Mircea R. Stan, Wayne P. Burleson
    Low-power encodings for global communication in CMOS VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:444-455 [Journal]
    
17. Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu
    Wave-pipelining: a tutorial and research survey. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:464-474 [Journal]
    
18. Bongjin Jung, Wayne P. Burleson
    Efficient VLSI for Lempel-Ziv compression in wireless data communication networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:475-483 [Journal]
    
19. Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems
    The spring scheduling coprocessor: a scheduling accelerator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:38-47 [Journal]
    
20. 
    Analysis and mitigation of process variation impacts on Power-Attack Tolerance. [Citation Graph (, )][DBLP]
    
    
21. 
    Multicore soft error rate stabilization using adaptive dual modular redundancy. [Citation Graph (, )][DBLP]
    
    
22. 
    Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors. [Citation Graph (, )][DBLP]
    
    
23. 
    Thermal-aware voltage droop compensation for multi-core architectures. [Citation Graph (, )][DBLP]
    
    
24. 
    Circuit-level NBTI macro-models for collaborative reliability monitoring. [Citation Graph (, )][DBLP]
    
    
25. 
    Calibration of on-chip thermal sensors using process monitoring circuits. [Citation Graph (, )][DBLP]
    
    
26. 
    Low power on-chip thermal sensors based on wires. [Citation Graph (, )][DBLP]
    
    
27. 
    Temperature measurement in Content Addressable Memory cells using bias-controlled VCO. [Citation Graph (, )][DBLP]