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Frédéric Bancel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
    A secure scan design methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1177-1178 [Conf]
  2. David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell
    Scan Design and Secure Chip. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:219-226 [Conf]
  3. David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
    Secure Scan Techniques: A Comparison. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:119-124 [Conf]
  4. Nicolas Valette, Lionel Torres, Gilles Sassatelli, Frédéric Bancel
    Securing embedded programmable gate arrays in secure circuits. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  5. Yves Bertrand, Frédéric Bancel, Michel Renovell
    Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:989-997 [Conf]
  6. Nicolas Valette, Lionel Torres, Frédéric Bancel, Nicolas Bérard
    Integration of Reconfigurable Logic on Secure Circuits. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:163-168 [Conf]
  7. Yves Bertrand, Frédéric Bancel, Michel Renovell
    A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:51-54 [Conf]
  8. Olivier Faurax, Assia Tria, Laurent Freund, Frédéric Bancel
    Robustness of circuits under delay-induced faults : test of AES with the PAFI tool. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:185-186 [Conf]

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