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Publications of Author

1. Yi-Lin Hsieh, Tsai-Ming Hsieh
   A New Effective Congestion Model in Floorplan Design. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1204-1209 [Conf]
   
2. Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chun-Chiao Chang, Tsai-Ming Hsieh
   A New Formulation for SOC Floorplan Area Minimization Problem. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:1100- [Conf]
   
3. Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh
   Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). [Citation Graph (0, 0)][DBLP]
   FPGA, 2000, pp:217- [Conf]
   
4. Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh
   Floorplanning with clock tree estimation. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 2005, pp:6244-6247 [Conf]
   
5. Chin-Hui Wang, Yung-Ching Chen, Tsai-Ming Hsieh, Chih-Hung Lee, Hsin-Hsiung Huang
   A new congestion and crosstalk aware router. [Citation Graph (0, 0)][DBLP]
   ISCAS (6), 2005, pp:6234-6237 [Conf]
   
6. Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh
   Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2001, pp:519-522 [Conf]
   
7. Chih-Hung Lee, Yi-Lin Hsieh, Hui-Chun Lee, Tsai-Ming Hsieh
   Sequence-pair based placement with boundary constraints. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2002, pp:341-344 [Conf]
   
8. Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh
   Structural Decomposition with Functional Considerations for Low Power. [Citation Graph (0, 0)][DBLP]
   ISQED, 2002, pp:464-469 [Conf]
   
9. Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh
   A congestion-driven buffer planner with space reservation. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
10. 
    Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. [Citation Graph (, )][DBLP]
    
    
11. 
    Timing-driven X-architecture router among rectangular obstacles. [Citation Graph (, )][DBLP]
    
    
12. 
    An efficient hierarchical approach for general floorplan area minimization. [Citation Graph (, )][DBLP]