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Dariusz Kania: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dariusz Kania
    Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1087- [Conf]
  2. Robert Czerwinski, Dariusz Kania
    State Assignment for PAL-based CPLDs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:127-134 [Conf]
  3. Dariusz Kania, Józef Kulisz, Adam Milik
    A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:114-121 [Conf]
  4. Dariusz Kania, Adam Milik, Józef Kulisz
    Decomposition of Multi-Output Functions for CPLDs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:442-449 [Conf]
  5. Dariusz Kania
    Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1138-1145 [Conf]
  6. Dariusz Kania
    A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1146-0 [Conf]
  7. Dariusz Kania
    Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1278-1281 [Conf]
  8. Dariusz Kania
    A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:152-155 [Conf]
  9. Dariusz Kania, Józef Kulisz
    Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2007, v:80, n:7, pp:1129-1141 [Journal]

  10. CPLD-oriented Synthesis of Finite State Machines. [Citation Graph (, )][DBLP]


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