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Luca Sterpone: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1290-1295 [Conf]
  2. Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante
    A new approach to compress the configuration information of programmable devices. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:48-51 [Conf]
  3. Oscar Ruano, Pilar Reyes, Juan A. Maestro, Luca Sterpone, Pedro Reviriego
    An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:261-266 [Conf]
  4. Luca Sterpone, Massimo Violante
    ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:54-58 [Conf]
  5. Luca Sterpone, Massimo Violante
    A design flow for protecting FPGA-based systems against single event upsets. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:436-444 [Conf]
  6. Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto
    Combined software and hardware techniques for the design of reliable IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:265-273 [Conf]
  7. Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante
    New evolutionary techniques for test-program generation for complex microprocessor cores. [Citation Graph (0, 0)][DBLP]
    GECCO, 2005, pp:2193-2194 [Conf]
  8. Luca Sterpone, Massimo Violante
    A new hardware architecture for performing the gridding of DNA microarray images. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:341-346 [Conf]
  9. Luca Sterpone, Massimo Violante
    A new decompression system for the configuration process of SRAM-based FPGAS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:241-246 [Conf]
  10. Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:115-120 [Conf]
  11. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    Efficient Estimation of SEU Effects in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:54-59 [Conf]
  12. Luca Sterpone, Massimo Violante
    Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:189-190 [Conf]
  13. Luca Sterpone, Massimo Violante
    A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:6, pp:732-744 [Journal]
  14. Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
    Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:194-196 [Conf]
  15. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena
    Fault Injection-based Reliability Evaluation of SoPCs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:75-82 [Conf]
  16. Luca Sterpone, Massimo Violante
    Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:159-164 [Conf]
  17. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  18. Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro
    Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:47-54 [Journal]

  19. Differential gene expression graphs: A data structure for classification in DNA microarrays. [Citation Graph (, )][DBLP]


  20. A graph-based representation of Gene Expression profiles in DNA microarrays. [Citation Graph (, )][DBLP]


  21. On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications. [Citation Graph (, )][DBLP]


  22. A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. [Citation Graph (, )][DBLP]


  23. A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs. [Citation Graph (, )][DBLP]


  24. Optimization of Self Checking FIR filters by means of Fault Injection Analysis. [Citation Graph (, )][DBLP]


  25. Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  26. Soft errors in Flash-based FPGAs: Analysis methodologies and first results. [Citation Graph (, )][DBLP]


  27. On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs. [Citation Graph (, )][DBLP]


  28. Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. [Citation Graph (, )][DBLP]


  29. An integrated flow for the design of hardened circuits on SRAM-based FPGAs. [Citation Graph (, )][DBLP]


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