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Publications of Author

1. Bram Kruseman, Manuel Heiligers
   On test conditions for the detection of open defects. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:896-901 [Conf]
   
2. Bram Kruseman, Peter Janssen, Victor Zieren
   Transient current testing of 0.25 /spl mu/m CMOS devices. [Citation Graph (0, 0)][DBLP]
   ITC, 1999, pp:47-56 [Conf]
   
3. Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger
   On Hazard-free Patterns for Fine-delay Fault Testing. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:213-222 [Conf]
   
4. Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede
   Systematic Defects in Deep Sub-Micron Technologies. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:290-299 [Conf]
   
5. Bram Kruseman, Stefan van den Oetelaar
   Detection of Resistive Shorts in Deep Sub-micron Technologies. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:866-875 [Conf]
   
6. Bram Kruseman, Stefan van den Oetelaar, Josep Rius
   Comparison of IDDQ Testing and Very-Low Voltage Testing. [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:964-973 [Conf]
   
7. Bram Kruseman, Rudger van Veen, Kees van Kaam
   The future of delta I_DDQ testing. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:101-110 [Conf]
   
8. Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge
   Trends in Testing Integrated Circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:688-697 [Conf]
   
9. D. Arumi, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
   Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. [Citation Graph (0, 0)][DBLP]
   VTS, 2007, pp:145-150 [Conf]
   
10. Bram Kruseman, Ananta K. Majhi, Guido Gronthoud
    On Performance Testing with Path Delay Patterns. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:29-34 [Conf]
    
11. Rosa Rodríguez-Montañés, D. Arumi, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi
    Diagnosis of Full Open Defects in Interconnecting Lines. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:158-166 [Conf]
    
12. 
    NIM- a noise index model to estimate delay discrepancies between silicon and simulation. [Citation Graph (, )][DBLP]
    
    
13. 
    Impact of Temperature on Test Quality. [Citation Graph (, )][DBLP]
    
    
14. 
    Full Open Defects in Nanometric CMOS. [Citation Graph (, )][DBLP]
    
    
15. 
    Diagnosis of full open defects in interconnect lines with fan-out. [Citation Graph (, )][DBLP]
    
    
16. 
    Modeling Power Supply Noise in Delay Testing. [Citation Graph (, )][DBLP]